SST26VF032BEUI datasheet(37/76 Pages) MICROCHIP

37 / 76 page

 2019 Microchip Technology Inc.

DS20006152A-page 37

SST26VF032BEUI

5.36

Non-Volatile Write-Lock Lock-

Down Register (nVWLDR)

The Non-Volatile Write-Lock Lock-Down Register

(nVWLDR) instruction controls the ability to change the

Write-Lock bits in the Block-Protection register. Exe-

cute WREN before initiating the nVWLDR instruction.

To execute nVWLDR, the host drives CE# low, then

sends the nVWLDR command cycle (E8H), followed by

18 cycles of data, and then drives CE# high.

After CE# goes high, the non-volatile bits are pro-

grammed and the programming time-out must com-

plete before any additional commands, other than

Read Status Register, can be entered. Poll the BUSY

bit in the Status register, or wait TPP, for the completion

of the internal, self-timed, Write operation. Data inputs

must be most significant bit(s) first.

FIGURE 5-42:

WRITE-LOCK LOCK-DOWN REGISTER SEQUENCE (SQI)

FIGURE 5-43:

WRITE-LOCK LOCK-DOWN REGISTER SEQUENCE (SPI)

20005218 F36.0

MODE 3

SCK

SIO(3:0)

CE#

MODE 0

H0 L0

MSN LSN

H1 L1

H2 L2

H3 L3

H4 L4

H5 L5

HN LN

BPR [m:m-7]

BPR [7:0]

Note:

MSN= Most Significant Nibble; LSN = Least Significant Nibble

Write-Lock Lock-Down Register (nVWLDR) m = 79

CE#

SCK

Data Byte0

01 2 3 4 5 6 7 8

Data Byte1

Data Byte2

Data ByteN

E8H

15 16

23 24

31 32

MODE 0

MODE 3

OP Code

20005218 F69.1

SST26VF032BEUI Datasheet(PDF) 37 Page - Microchip Technology

SST26VF032BEUI Datasheet(HTML) 37 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76

Datasheet Download

Link URL