SST26VF032BEUI datasheet(14/76 Pages) MICROCHIP

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SST26VF032BEUI

DS20006152A-page 14

 2019 Microchip Technology Inc.

5.1

No Operation (NOP)

The No Operation command only cancels a Reset

Enable command. NOP has no impact on any other

command.

5.2

Reset-Enable (RSTEN) and Reset

(RST)

The Reset operation is used as a system (software)

reset that puts the device in normal operating Ready

mode. This operation consists of two commands:

Reset-Enable (RSTEN) followed by Reset (RST).

To reset the SST26VF032BEUI, the host drives CE#

low, sends the Reset-Enable command (66H), and

drives CE# high. Next, the host drives CE# low again,

sends the Reset command (99H), and drives CE# high,

see Figure 5-1.

The Reset operation requires the Reset-Enable com-

mand followed by the Reset command. Any command

other than the Reset command after the Reset-Enable

command will disable the Reset-Enable.

Once the Reset-Enable and Reset commands are suc-

cessfully executed, the device returns to normal opera-

tion Read mode and then does the following: resets the

protocol to SPI mode, resets the burst length to 8

Bytes, clears all the bits, except for bit 4 (WPLD) and

bit 5 (SEC), in the Status register to their default states,

and clears bit 1 (IOC) in the configuration register to its

default state. A device reset during an active Program

or Erase operation aborts the operation, which can

cause the data of the targeted address range to be cor-

rupted or lost. Depending on the prior operation, the

reset timing may vary. Recovery from a Write operation

requires more latency time than recovery from other

operations. See Table 8-2 on page 45 for Rest timing

parameters.

FIGURE 5-1:

RESET SEQUENCE

5.3

Read (40 MHz)

The Read instruction, 03H, is supported in SPI bus pro-

tocol only with clock frequencies up to 40 MHz. This

command is not supported in SQI bus protocol. The

device outputs the data starting from the specified

address location, then continuously streams the data

output through all addresses until terminated by a low-

to-high transition on CE#. The internal address pointer

will automatically increment until the highest memory

address is reached. Once the highest memory address

is reached, the address pointer will automatically return

to the beginning (wrap-around) of the address space.

Initiate the Read instruction by executing an 8-bit com-

mand, 03H, followed by address bits A[23:0]. CE# must

remain active low for the duration of the Read cycle.

See Figure 5-2 for Read Sequence.

FIGURE 5-2:

READ SEQUENCE (SPI)

20005218 F05.0

MODE 3

CLK

SIO(3:0)

CE#

MODE 3

C3 C2

MODE 0

MODE 3

MODE 0

TCPH

Note: C[1:0] = 66H; C[3:2] = 99H

20005218 F29.0

CE#

SCK

ADD.

01 2 3 4 5 6 7 8

ADD.

HIGH IMPEDANCE

15 16

23 24

31 32

39 40

47 48

55 56

63 64

N+2

N+3

N+4

N+1

DOUT

MSB

MODE 0

MODE 3

DOUT

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