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ADAR4002ACPZ-R7 Datasheet(PDF) 51 Page - Analog Devices

Part # ADAR4002ACPZ-R7
Description  0.5 GHz to 19 GHz, 1-Channel, Bidirectional True Time Delay Unit
PDF  66 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADAR4002ACPZ-R7 Datasheet(HTML) 51 Page - Analog Devices

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Data Sheet
ADAR4002
REGISTER MAP
analog.com
Rev. A | 51 of 66
Table 14. ADAR4002 Register Summary (Continued)
Addr
Name
Bits Bit Name
Description
Reset Access
[6:0] FIRSTRANK_TIMEDELAY05
7-Bit Time Delay Control. Default = 0x00, minimum time
delay.
0x0
R/W
0x2B
DSA05
[7:2] FIRSTRANK_DSA05
6-Bit Attenuation Control. Default = 0x3F, maximum
attenuation.
0x3F
R/W
1
RESERVED
Reserved.
0x0
R
0
DATA_LOAD
Load Signal for Second Rank of Registers. This bit auto
clears after being set.
0x0
R/W
0x2C
TD06
7
FR_TDRANGE06
Time Delay Range. 0 = Range 0, 508 ps, and 1 = Range 1,
254 ps.
0x0
R/W
[6:0] FIRSTRANK_TIMEDELAY06
7-Bit Time Delay Control. Default = 0x00, minimum time
delay.
0x0
R/W
0x2D
DSA06
[7:2] FIRSTRANK_DSA06
6-Bit Attenuation Control. Default = 0x3F, maximum
attenuation.
0x3F
R/W
1
RESERVED
Reserved.
0x0
R
0
DATA_LOAD
Load Signal for Second Rank of Registers. This bit auto
clears after being set.
0x0
R/W
0x2E
TD07
7
FR_TDRANGE07
Time Delay Range. 0 = Range 0, 508 ps, and 1 = Range 1,
254 ps.
0x0
R/W
[6:0] FIRSTRANK_TIMEDELAY07
7-Bit Time Delay Control. Default = 0x00, minimum time
delay.
0x0
R/W
0x2F
DSA07
[7:2] FIRSTRANK_DSA07
6-Bit Attenuation Control. Default = 0x3F, maximum
attenuation.
0x3F
R/W
1
RESERVED
Reserved.
0x0
R
0
DATA_LOAD
Load Signal for Second Rank of Registers. This bit auto
clears after being set.
0x0
R/W
0x30
TD08
7
FR_TDRANGE08
Time Delay Range. 0 = Range 0, 508 ps, and 1 = Range 1,
254 ps.
0x0
R/W
[6:0] FIRSTRANK_TIMEDELAY08
7-Bit Time Delay Control. Default = 0x00, minimum time
delay.
0x0
R/W
0x31
DSA08
[7:2] FIRSTRANK_DSA08
6-Bit Attenuation Control. Default = 0x3F, maximum
attenuation.
0x3F
R/W
1
RESERVED
Reserved.
0x0
R
0
DATA_LOAD
Load Signal for Second Rank of Registers. This bit auto
clears after being set.
0x0
R/W
0x32
TD09
7
FR_TDRANGE09
Time Delay Range. 0 = Range 0, 508 ps, and 1 = Range 1,
254 ps.
0x0
R/W
[6:0] FIRSTRANK_TIMEDELAY09
7-Bit Time Delay Control. Default = 0x00, minimum time
delay.
0x0
R/W
0x33
DSA09
[7:2] FIRSTRANK_DSA09
6-Bit Attenuation Control. Default = 0x3F, maximum
attenuation.
0x3F
R/W
1
RESERVED
Reserved.
0x0
R
0
DATA_LOAD
Load Signal for Second Rank of Registers. This bit auto
clears after being set.
0x0
R/W
0x34
TD10
7
FR_TDRANGE10
Time Delay Range. 0 = Range 0, 508 ps, and 1 = Range 1,
254 ps.
0x0
R/W
[6:0] FIRSTRANK_TIMEDELAY10
7-Bit Time Delay Control. Default = 0x00, minimum time
delay.
0x0
R/W
0x35
DSA10
[7:2] FIRSTRANK_DSA10
6-Bit Attenuation Control. Default = 0x3F, maximum
attenuation.
0x3F
R/W
1
RESERVED
Reserved.
0x0
R



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