ADAR4002ACPZ-R7 datasheet(11/66 Pages) AD

11 / 66 page

Data Sheet

ADAR4002

SPECIFICATIONS

analog.com

Rev. A | 11 of 66

SHIFT REGISTER MODE

The ADAR4002 offers an extremely simple serial shift register mode by asserting the MODE pin high. In this mode, there are no register

addresses, no sequencer functionality, and no short commands. The shift register has dual rank data registers and is controlled with the

UPDATE pin. The digital pins of the ADAR4002 are configured for a daisy-chain operation, with the possibility of one ADAR4002 driving

another, in as long a chain as required. Data comes in on CLK_IN and DATA_IO and shifts out on CSB/CLKO and DATA_O. Data is serially

shifted through the full chain of the devices. Once the correct TDU and DSA data are in the correct devices, an update signal is given to load

the data into the second rank register of the several devices. The second rank register data is immediately applied to the various TDUs and

DSAs on all the daisy chained ADAR4002 devices. Shift register mode timing is shown in Figure 8.

Figure 8. Timing Diagram for Two ADAR4002 Chips Daisy-Chained Together While in Shift Register Mode (Chip 1 Drives Chip 2)

ADAR4002ACPZ-R7 Datasheet(PDF) 11 Page - Analog Devices