OR3LP26B datasheet(83/184 Pages) AGERE

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Lucent Technologies Inc.

Data Sheet

ORCA OR3LP26B FPSC

March 2000

Embedded Master/Target PCI Interface

Lucent Technologies Inc.

PCI Bus Core Detailed Description Quad Port (continued)

Embedded Core Bit Stream Configurable Options

Table 27 lists all optional functionality in the PCI core that can be defined via bits in the FPGA configuration RAM.

The table also lists the settings available for each feature. Each of these options is configured using the FPSC

Design Kit software.

Table 27. PCI Core Options Settable via FPGA Configuration RAM Bits

Address in

Configuration Space

Optional Settings

Revision ID

Any 8-bit value.

Class Code

09—0B

Any 24-bit value.

Bus Master Support

Command register bit 2

Four options.

Initially disabled, read-only.

Initially disabled, read/write.

Initially enabled, read-only.

Report: Data Parity Error Detected

Status register bit 8

Include or exclude in decode for pci_mcfg_stat.

Report: Target Abort Signaled

Status register bit 11

Include or exclude in decode for pci_tcfg_stat.

Report: Target Abort Received

Status register bit 12

Include or exclude in decode for pci_mcfg_stat.

Report: Master Abort Received

Status register bit 13

Include or exclude in decode for pci_mcfg_stat.

Report: System Error Signaled

Status register bit 14

Include or exclude in decode for pci_tcfg_stat.

Report: Parity Error Detected

(nonmaskable)

Status register bit 15

Include or exclude in decode for pci_tcfg_stat.

Latency Timer Initial Value

Any 8-bit value divisible by 8.

Base Address Register (BAR) Area 1

10—17

One or two 32-bit BARs or one 64-bit BAR, or none

(i.e., unprogrammed).

If 64-bit BAR, must be memory; page size can be from

24 to 264 bytes.

32-bit BARs can be memory or I/O.

If 32-bit I/O BAR, page size can be from 22 to 232 bytes.

If 32-bit memory BAR, address space can be 220 or 232

bytes, page size can be 24 to the maximum (220 or 232)

bytes.

If memory, can be prefetchable or nonprefetchable.

Base Address Register (BAR) Area 2

18—1F

Same as for BAR area 1.

Base Address Register (BAR) Area 3

20—27

Same as for BAR area 1.

Subsystem Vendor ID

2C—2D

Any 16-bit value.

Subsystem ID

2E—2F

Any 16-bit value.

Minimum Grant (Min_Gnt)

Any 8-bit value.

Maximum Latency (Max_Lat)

Any 8-bit value.

Port Mode

—

Dual port or quad port.

I/O Mode

—

Fast or slew-limited PCI output buffers.

Master FIFO Interface Clock

—

fclk1 or fclk2.

Target FIFO Interface Clock

—

fclk1 or fclk2.

Target Address Comparator

—

Enabled or disabled; when enabled, PCI core will not

transfer most significant byte(s) of Target address if they

match previous Target operation's address and require

additional bus cycle(s).

Target Maximum Intial Latency

—

Normal (16) or extended (32); note that only normal

latency complies with PCI Specification. Extended latency

may be specified in proprietary systems where bandwidth

requirements override fairness considerations.

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