OR3LP26B datasheet(16/184 Pages) AGERE

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Lucent Technologies Inc.

ORCA OR3LP26B FPSC

Data Sheet

Embedded Master/Target PCI Interface

March 2000

Lucent Technologies Inc.

PCI Bus Core Detailed Description

(continued)

PCI Protocol Fundamentals

Basic Transfer Control

The following paragraphs describe various aspects of

the PCI protocol and the way they are handled by the

PCI core.

Addressing. The PCI Specification defines three types

of address spaces. The first, configuration address

space, is a physical address of space and is intended

as a means for powerup software to identify agents and

configure them before other address spaces have allo-

cated. The second, I/O address space, is intended for

mapping control functions. Control function page sizes

in configuration space should be no more than

256 bytes. The third, memory address space, is

intended for bulk data transfer. It has features to facili-

tate this, such as special commands for cache imple-

mentation, large page sizes, and mechanisms for

prefetching. The PCI core handles all three address

space types as both a Master and a Target.

Byte Alignment. On all write operations (configuration,

I/O, and memory space, and including the memory

write and invalidate instruction), for both the PCI core’s

Master and Target functions, byte enables are fully

implemented from/to the FPGA interface. Note, how-

ever, that even though the PCI core implements the

ability to control byte enables for the memory write and

invalidate instruction, the PCI Specification requires

that this instruction assert all byte enables, and this is

the FPGA application’s responsibility. On read opera-

tions, the utility of byte enables is more dubious since

the data must be enroute from the PCI bus from Target

to Master, at the time that the corresponding byte

enables are enroute on the PCI bus Master to Target

(unless wait-states are inserted). The PCI core, there-

fore, does not implement byte enable control for Master

or Target reads. Byte enables on master read opera-

tions are always asserted, and target ignores the byte

enables that are sent, in accordance with PCI Specifi-

cation requirements.

Device Selection (devseln)

The target is responsible for responding to a master’s

request by asserting the PCI bus signal devseln.

devseln may be asserted one, two, or three clocks

after the address phrase of a transaction, correspond-

ing to fast, medium, or slow decode, respectively. The

PCI core’s target is capable of preforming a medium-

speed decode response. The decode response speed

has a significant impact on the overall latency and

bandwidth of nonburst PCI transactions, but its impact

decreases greatly for burst transactions, particularly for

burst lengths of the size of the PCI core’s FIFOs.

Address/Data Stepping

Stepping is an optional feature added to the PCI Speci-

fication to accommodate agents whose bus drive capa-

bility is insufficient to handle large groups of signals

changing state in one clock cycle. Continuous stepping

allows weak drivers multiple cycles for signal transition.

Discrete stepping partitions the bus into two or more

groups of bits that transition on successive clock

cycles. However, stepping exacts a heavy toll on perfor-

mance, cutting maximum bandwidth by at least 50%

and increasing latency. The PCI core is designed for

maximum throughput with high-performance buffers, so

stepping is unnecessary and not implemented. The

wait cycle control, bit 7 of the command register, is

therefore hardwired to a zero.

Reset Operation

The PCI bus contains a signal, rstn, that performs a

PCI reset function. When the reset occurs, all state

machines in the ASIC are placed in their idle state, the

configuration space BARs are reset to their mask val-

ues, and the command registers are reset. The reset

does not reset the FPGA logic. The PCI reset signal is

fed from the ASIC to the FPGA logic to be used by the

designer.

Interrupt Acknowledge

The interrupt acknowledge command is a read by the

system CPU implicitly addressed to the system inter-

rupt controller. Other agents, including the PCI core,

are not required to implement this instruction; the PCI

core’s Master does not generate it and its Target

ignores it.

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