OR3LP26B datasheet(42/184 Pages) AGERE

42 / 184 page

Lucent Technologies Inc.

ORCA OR3LP26B FPSC

Data Sheet

Embedded Master/Target PCI Interface

March 2000

Lucent Technologies Inc.

PCI Bus Core Detailed Description Dual

Port (continued)

Master (FPGA Initiated) Read

Operation Setup

In order to initiate a PCI Master read operation, the

FPGA application must supply the required information

in the specific order prescribed in Table 19 through

Table 20. The command word, burst length, and

address must be accompanied by assertion of the

enable maenn. The definition of the Master command

word was previously described in Table 10. The FPGA

application can use the value returned on bus mstate-

cntr, the Master state counter’s present value, to deter-

mine the counter’s next state, using the state diagram

for the particular operation being executed. The

counter’s next state must be determined because the

FPGA application must supply the data to the PCI core

that corresponds to the counter value being sent from

the core to the FPGA.

Data Transfer

The FPGA application begins receiving the read data

by deasserting maenn and asserting mrdataenn. On

every cycle that mrdataenn is asserted, the PCI core

clocks data from the Master read FIFO (64 deep by

36 bits wide in 32-bit PCI mode; 32 deep by 72 bits

wide in 64-bit PCI mode) to the FPGA application via

bus datatofpga.

FIFO Empty/Almost Empty

When the Master read FIFO contains four or fewer data

elements, the PCI core asserts mr_aemptyn, the

almost empty indicator. This allows some latency to

exist in the FPGA’s response without risking overread-

ing the FIFO. When all locations in the Master write

FIFO are empty, the PCI core asserts mr_empty, the

FIFO empty indicator. Since data can be simulta-

neously written to and read from the Master read FIFO,

both mr_aemptyn and mr_emptyn can change states

in either direction multiple times in the course of a burst

data transfer.

FIFO Full

In addition to the empty and almost empty signals that

report when the Master read FIFO is currently unable

to supply data to the FPGA application, the PCI core

also provides the FIFO's full signal. During a master

read burst transaction, the master read FIFO may go

full, especially if the user side application is slow at

unloading the FIFO. When this condition occurs, the

master will insert wait-states continuously until another

word is read from the FIFO, or the word count is

exhausted. On the target side, if the target is ready to

send more data, it will have trdyn asserted which will

disable it from terminating the transaction as well. This

can create a deadlock condition on the PCI bus. If the

user application cannot unload any more data, and

wishes to terminate the burst, additional FPGA logic

must be incorporated to detect and accomplish the ter-

mination. Two operations must occur to terminate the

current transaction. First, the fpga_mstopburstn sig-

nal must be asserted indicating to the core the master

request to terminate. Second, one additional word of

data must be read from the FIFO (only if the FIFO is

full). The signal fpga_mstopburstn needs to stay

asserted low until the ma_fulln flag is asserted low

indicating that the transaction has been terminated and

cleared.

Designing a Deadlock Timer

This design example is a method by which the user

application can detect this condition and terminate the

burst transaction. Since the mr_fulln and

fpga_mstopburstn signals are on the pciclk clock

domain, the deadlock counter will run on the pciclk

clock. The mr_fulln signal is fed as a clock enable and

a synchronous clear to a counter, driven by pciclk. The

counter's length may be designed to guarantee a cer-

tain time-out latency on the PCI bus. When the FIFO is

not full (mr_fulln = 1), the counter will stay cleared.

When the FIFO has been full for an extended period of

time, the counter will count and eventually overflow.

This overflow indication can be used to set the

fpga_mstopburstn signal indicating a request to stop

the burst. The overflow signal is then detected and syn-

chronized onto the fclk domain to be used to read one

additional word from the FIFO. The transaction will

complete, and the core will go back into an idle state.

Bursting

The PCI core uses the burst count supplied during

operation setup to determine the Master read opera-

tion’s burst length (unlike the Master write, which uses

signal mwlastcycn). The burst length of 18 bits allows

bursts of up to 218–1 quad words to be specified. To ini-

tiate a burst, the starting address must be aligned to a

64-byte boundary, and all of the byte enables must be

enabled. If ad[2] is a 1, a single transfer will executed.

OR3LP26B Datasheet(PDF) 42 Page - Agere Systems

OR3LP26B Datasheet(HTML) 42 Page - Agere Systems

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL