OR3LP26B datasheet(59/184 Pages) AGERE

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Lucent Technologies Inc.

Data Sheet

ORCA OR3LP26B FPSC

March 2000

Embedded Master/Target PCI Interface

Lucent Technologies Inc.

PCI Bus Core Detailed Description Dual

Port (continued)

Delayed Transactions

Delayed transactions can be executed by assesting

deltrn low. When deltrn is asserted low, the PCI core

Target read logic will issue a retry whenever no Target

read operation is already pending. When this signal is

inactive-high, it will instead generate wait-states, and

continue to do so until either the FIFO becomes not

empty, when it will transmit the data, or until the maxi-

mum initial latency value (16 or 32 clock cycles) has

been reached. This signal should be inactive when

minimum latency is desired on the initial data word, at

the expense of overall PCI bus efficiency. Whereas dis-

able delayed transactions affects the transaction’s

behavior on the initial data word, signal trburstpendn

affects behavior when the Target read FIFO empties.

When trburstpendn is inactive, a disconnect without

data results from an attempt to read from an empty

FIFO. With trburstpendn active, the PCI core will wait

for data from the FIFO by inserting wait-states (up to

the maximum subsequent latency value of 8, at which

time a disconnect without data will be generated).

Asserting trburstpendn will minimize latency for this

transaction’s data at the expense of overall PCI bus

efficiency. trburstpendn must remain static throughout

a Target read transaction.

Delayed transactions are very similar to a target retry

except that the address is actually stored in the core.

Delayed transactions are usually implemented in sys-

tems where the user side interface cannot supply the

first piece of data in 16 clock cycles. An example of this

may be that the user interface is connected to another

bus system. On a PCI target read, the user interface

must arbitrate for the user bus and get the necessary

data. Delayed transaction mode is used when the del-

trn bit is asserted low. This bit is not a dynamic bit. It

must be set ahead of a transaction occurring. It is not

recommended to switch between delayed and non-

delayed transactions dynamically.

When deltrn is low, a master read request is termi-

nated in a target retry. On the user interface side, the

address is stored in the target address FIFO, and treqn

is asserted low. All future master requests are termi-

nated in a retry until the address is read out of the

FIFO, data is loaded into the FIFO, and the same

request comes back to complete the transaction. In

generating this signal, keep in mind that this signal

needs to be synchronous to pciclk.

Another option the designer has using delayed transac-

tions is to use the signal trpcihold. The signal trpci-

hold should be used when the user side interface is

slow loading requested data, and the designer wishes

to utilize the PCI in the most efficient manner. Without

this signal, an external master will request data and

hold onto the PCI bus until either it has received it or it

gets terminated by latency timers, etc. A more efficient

method to utilize the PCI bus is to assert trpcihold,

load the FIFOs, and then deassert it. While the trpci-

hold signal is asserted, the core thinks that the FIFOs

stay empty even though they are slowly filling with data.

Requests from an external master are terminated in

retries. When the trpcihold signal is deasserted (or the

FIFO becomes full), the core will allow an external

master to come in, the data will be burst across the PCI

bus as fast as the master will allow, and the transaction

will end. In generating trpcihold, keep in mind that this

signal needs to be synchronous to pciclk.

Termination

Normal transaction completion occurs immediately

upon completion of the PCI bus transfer, even if extra

data remains in the Target read FIFO. When the PCI

transaction ends either normally, or as retry, discon-

nect, or Target abort, the PCI core signals end of trans-

action to the FPGA application by deasserting treqn.

When treqn deasserts, the FPGA application must

immediately deassert trdataenn.

OR3LP26B Datasheet(PDF) 59 Page - Agere Systems

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