OR3LP26B datasheet(5/184 Pages) AGERE

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Lucent Technologies Inc.

Data Sheet

ORCA OR3LP26B FPSC

March 2000

Embedded Master/Target PCI Interface

Lucent Technologies Inc.

PCI Bus Core Highlights (continued)

Master:

— Generates all defined command codes except

interrupt acknowledge and special cycle.

— Capable of accessing its own local Target.

— Capable of acting as the system's configuration

agent by booting up with the Master logic

enabled.

— Supports multiple options for Master bus requests,

to increase PCI bus bandwidth.

— Supports single-cycle I/O space accesses.

— Provides option to delay PCI access until FIFO is

full on Master writes to increase PCI bandwidth.

— Supports programmable latency timer control.

Target:

— Responds legally to all command codes: interrupt

acknowledge, special cycle, and reserved com-

mands ignored; memory read multiple and line

handled as memory read; memory write and

invalidate handled as memory write.

— Implements Target abort, disconnect, retry, and

wait cycles.

— Handles delayed transactions.

— Handles fast back-to-back transactions.

— Method of handling retries is programmable at

FPGA configuration to allow tailoring to different

Target data access latencies.

— Decodes at medium speed.

— Provides option to delay PCI access until FIFO is

full on Target reads to increase PCI bandwidth.

Supports dual-address cycles (both as Master and

Target).

Supports all six base address registers (BARs), as

either memory (32-bit or 64-bit) or I/O. Any legal

page size can be independently specified for each

BAR during FPGA configuration.

Independent Master and Target clocks can be sup-

plied to the PCI FIFO interface from the FPGA-based

logic.

Provides versatile clocking capabilities with FPGA

clocks sourced from PCI bus clock or elsewhere.

FIFO interface buffers asynchronous clock domains

between the PCI interface and FPGA-based logic.

PCI interface timing: meets or exceeds 33 MHz,

50 MHz, and 66 MHz PCI requirements.

Configuration options:

— Class code, revision ID.

— Latency timer.

— Cache line size.

— Subsystem ID.

— Subsystem vendor ID.

— Maximum latency, minimum grant.

— Interrupt line.

— Hot Plug/Hot Swap capability.

Generates interrupts on intan as directed by the

FPGA.

PCI I/O output drivers can be programmed for fast or

slew-limited operation.

Automatically detects 5 V or 3.3 V PCI bus signaling

environment and provides appropriate I/O signaling,

under 3.3 V commercial conditions.

Ideally suited for such applications as:

— PCI-based graphics/video/multimedia.

— Bridges to ISA/EISA/MCA, LAN, SCSI, Ethernet,

ATM, or other bus architectures.

— High-bandwidth data transfer in proprietary sys-

tems.

FPSC Highlights

Implemented as an embedded core into the

advanced Series 3+

ORCA FPSC architecture.

Allows the user to integrate the core with up to 120K

gates of programmable logic, all in one device, and

provides up to 259 user I/O pins in addition to the

PCI interface pins.

FPGA portion retains all of the features of the

ORCA

3 FPGA architecture:

— High-performance, cost-effective, 0.25 µm

5-level metal technology.

— Twin-quad programmable function unit (PFU)

architecture with eight 16-bit look-up tables

(LUTs) per PFU, organized in two nibbles for use

in nibble- or byte-wide functions. Allows for mixed

arithmetic and logic functions in a single PFU.

Parameter

33 MHz

50 MHz

66 MHz

Device Clock = > Out

11.0 ns

7.5 ns

6.0 ns

Device Setup Time

7.0 ns

4.5 ns

3.0 ns

Board Prop. Delay

10.0 ns

6.5 ns

5.0 ns

Board Clock Skew

2.0 ns

1.5 ns

1.0 ns

Total Budget

30.0 ns

20.0 ns

15.0 ns

Load Capacitance

50 pF

10 pF

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