OR3LP26B datasheet(46/184 Pages) AGERE

46 / 184 page

ORCA OR3LP26B FPSC

Data Sheet

Embedded Master/Target PCI Interface

March 2000

Lucent Technologies Inc.

PCI Bus Core Detailed Description Dual Port (continued)

Master Read, Burst Transaction

Figure 8 (FPGA bus dual port) and Figure 9 (PCI bus) show the timing of a four Quadword Master read burst. Oper-

ation is similar to that in the Master read, nonburst transaction, but extra data words are supplied by the FPGA

application. In Figure 8, the transaction is initiated by the FPGA application asserting Master address enable

(maenn), while providing the command, burst length, and lower DWORD address on bus datafmfpga. On the next

clock, the FPGA application provides the upper DWORD address and asserts mwlastcycn. On the third cycle,

both maenn and mwlastcycn are deasserted. PCI bus activity now begins as shown in Figure 9. Once data is

transferred on the PCI bus and mr_emptyn is deasserted high, the FPGA application asserts mrdataenn and four

Quadwords of data are transferred on bus datatofpga.

5-8834(F).a

Figure 8. Master Read 32-Byte Burst (FPGA Bus, Dual-Port, Burst Length, and 64-Bit Address)

TN+1

TN+2

TN+3

TN+4

TN+5

TN+6

CMD

BRST

ADRS

fclk

ma_fulln

mstatecntr

mcmd

datafmfpga

datatofpga

maenn

mrdataenn

mwlastcycn

mrlastcycn

mr_emptyn

mr_aemptyn

OR3LP26B Datasheet(PDF) 46 Page - Agere Systems