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AD9920ABBCZ Datasheet(PDF) 105 Page - Analog Devices

Part # AD9920ABBCZ
Description  12-Bit CCD Signal Processor with V-Driver and Precision Timing Generator
PDF  112 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9920ABBCZ Datasheet(HTML) 105 Page - Analog Devices

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AD9920A
Rev. B | Page 105 of 112
Address
Data
Bits
Default
Value
Update
Type
Name
Description
0xBA
[27:0]
0
UNUSED
Do not access, or write to 0x00.
0xBB
[27:0]
0
UNUSED
Do not access, or write to 0x00.
0xBC
[27:0]
0
UNUSED
Do not access, or write to 0x00.
0xBD
[27:0]
0
UNUSED
Do not access, or write to 0x00.
0xBE
[27:0]
0
UNUSED
Do not access, or write to 0x00.
0xBF
[27:0]
0
UNUSED
Do not access, or write to 0x00.
Table 61. Extra Registers
Address
Data Bits
Default Value
Update
Name
Description
0xC0
[27:0]
0
VD
Test
Do not access, or write to 0x00.
0xC1
[27:0]
0
VD
Test
Do not access, or write to 0x00.
0xC2
[27:0]
0
VD
Test
Do not access, or write to 0x00.
0xC3
[7:0]
0
SCK
GPO_MASK_HIGH
1 = masks GPO[x] to high. Takes priority over normal operation.
[15:8]
0
GPO_MASK_LOW
1 = masks GPO[x] to low. Takes priority over normal operation and
GPO_MASK_HIGH.
0xC4
[27:0]
0
VD
Test
Test register. Do not access, or set to 0.
0xC5
[27:0]
0x1516
SCK
Test
Test register. Do not access, or set to 0x1516.
0xC6
[27:0]
0
UNUSED
Unused register. Do not access, or set to 0.
0xC7
[27:0]
0
UNUSED
Unused register. Do not access, or set to 0.
0xC8
[27:0]
0
SCK
Test
Test register. Do not access, or set to 0.
0xC9
[27:0]
0xFFFF
SCK
Test
Test register. Do not access, or set to 0xFFFF.
0xCA
[27:0]
0
SCK
Test
Test register. Do not access, or set to 0.
0xCB
[27:0]
0
SCK
Test
Test register. Do not access, or set to 0.
0xCC
[27:0]
0
UNUSED
Unused register. Do not access, or set to 0.
0xCD
[27:0]
0
UNUSED
Unused register. Do not access, or set to 0.
0xCE
[27:0]
0
UNUSED
Unused register. Do not access, or set to 0.
0xCF
[27:0]
0
UNUSED
Unused register. Do not access, or set to 0.
0xD0
[27:0]
0
SCK
Test
Test register. Do not access, or set to 0.
0xD1
[19:0]
0
SCK
Test
Test use only. Set to 0.
[20]
0
STARTUP
Must be set to 1 to start the device.
0xD2
[27:0]
0
SCK
Test
Test register. Do not access, or set to 0.
0xD3
[27:0]
0
SCK
Test
Test register. Do not access, or set to 0.
0xD4
[0]
0
SCK
Test
Test use only. Set to 0.
[1]
0
GPO_INT_EN
1 = allow observation of internal signals at GPO1 to GPO3 outputs
(must also set SEL_GPx bits low).
Note that GPO4 to GPO8 continue to output normal GP toggles.
GPO1: internal clock.
GPO2: CLPOB.
GPO3: delayed sample clock.
[9:2]
0
Test
Test use only. Set to 0.
0xD5
[27:0]
0
SCK
Test
Test use only. Set to 0.
0xD6
[27:0]
0xA10
SCK
Test
Test use only. Set to 0xA10.
0xD7
[27:0]
0
SCK
Test
Test use only. Set to 0.
0xD8
[27:0]
0x888
SCK
DOUT_STRENGTH
Controls drive strength of data output drivers.
0x888 = normal drive strength.
0x848 = weak drive strength.
0x808 = weaker drive strength.
0xD9
[27:0]
0
SCK
Test
Test use only. Set to 0.
0xDA
[27:0]
0
SCK
Test
Test use only. Set to 0.
0xDB
[27:0]
SCK
Test
Test use only. Set to 0.
0xDC
[27:0]
0xF7F
SCK
Test
Test use only. Set to 0xF7F.
0xDD
[27:0]
0x14
SCK
Test
Test use only. Set to 0x14.



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