SPC564A80L7 datasheet(106/157 Pages) STMICROELECTRONICS

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Electrical characteristics

SPC564A74L7, SPC564A80B4, SPC564A80L7

106/157

Doc ID 15399 Rev 9

3.11

Temperature sensor electrical characteristics

3.12

eQADC electrical characteristics

fVCO self clock range is 20–150 MHz. fSCM represents fSYS after PLL output divider (ERFD) of 2 through 16 in enhanced

mode.

This value is determined by the crystal manufacturer and board design.

Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fSYS.

Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise

injected into the PLL circuitry via VDDPLL and VSSPLL and variation in crystal oscillator frequency increase the CJITTER

percentage for a given interval.

Proper PC board layout procedures must be followed to achieve specifications.

Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of CJITTER and either

fCS or fDS (depending on whether center spread or down spread modulation is enabled).

10. This value is determined by the crystal manufacturer and board design. For 4 MHz to 40 MHz crystals specified for this

PLL, load capacitors should not exceed these limits.

11. Proper PC board layout procedures must be followed to achieve specifications.

12. This parameter is guaranteed by design rather than 100% tested.

13. VIHEXT cannot exceed VRC33 in external reference mode.

14. This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the

synthesizer control register (SYNCR).

15. Modulation depth will be attenuated from depth setting when operating at modulation frequencies above 50 kHz.

Table 27.

Temperature sensor electrical characteristics

Symbol

Parameter

Conditions

Value

Unit

min

typical

max

—CC

Temperature

monitoring range

–40

—

150

°C

—

C Sensitivity

—

6.3

—

mV/°C

—

Accuracy

TJ = –40 to 150 °C

–10

—

°C

Table 28.

eQADC conversion specifications (operating)

Symbol

Parameter

Value

Unit

min

max

fADCLK

—

ADC clock (ADCLK) frequency

MHz

Conversion cycles

2+13

128+14

ADCLK cycles

TSR

Stop mode recovery time(1)

—10

s

fADCLK

—

ADC clock (ADCLK) frequency

Stop mode recovery time is the time from the setting of either of the enable bits in the ADC Control Register to the time that

the ADC is ready to perform conversions.Delay from power up to full accuracy = 8 ms.

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