SPC564A80L7 datasheet(20/157 Pages) STMICROELECTRONICS

20 / 157 page

Introduction

SPC564A74L7, SPC564A80B4, SPC564A80L7

20/157

Doc ID 15399 Rev 9

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Microinstructions now provide an option to issue Interrupt and Data Transfer requests

selected by channel. They can also be requested simultaneously at the same

instruction.

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Channel Flags 0 and 1 can now be tested for branching, in addition to selecting the

entry point.

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Channel digital filters can be bypassed.

The eTPU2 includes these distinctive features:

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32 channels; each channel associated with one input and one output signal

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Enhanced input digital filters on the input pins for improved noise immunity

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Identical, orthogonal channels: each channel can perform any time function. Each

time function can be assigned to more than one channel at a given time, so each

signal can have any functionality.

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Each channel has an event mechanism which supports single and double action

functionality in various combinations. It includes two 24-bit capture registers, two

24-bit match registers, 24-bit greater-equal and equal-only comparators.

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Input and output signal states visible from the host

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2 independent 24-bit time bases for channel synchronization:

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First time base clocked by system clock with programmable prescale division from

2 to 512 (in steps of 2), or by output of second time base prescaler

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Second time base counter can work as a continuous angle counter, enabling

angle based applications to match angle instead of time

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Both time bases can be exported to the eMIOS timer module

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Both time bases visible from the host

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Event-triggered microengine:

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Fixed-length instruction execution in two-system-clock microcycle

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14 KB of code memory (SCM)

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3 KB of parameter (data) RAM (SPRAM)

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Parallel execution of data memory, ALU, channel control and flow control sub-

instructions in selected combinations

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32-bit microengine registers and 24-bit wide ALU, with 1 microcycle addition and

subtraction, absolute value, bitwise logical operations on 24-bit, 16-bit, or byte

operands, single-bit manipulation, shift operations, sign extension and conditional

execution

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Additional 24-bit Multiply/MAC/Divide unit which supports all signed/unsigned

Multiply/MAC combinations, and unsigned 24-bit divide. The MAC/Divide unit

works in parallel with the regular microcode commands.

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Resource sharing features support channel use of common channel registers, memory

and microengine time:

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Hardware scheduler works as a “task management” unit, dispatching event

service routines by predefined, host-configured priority

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Automatic channel context switch when a “task switch” occurs, that is, one function

thread ends and another begins to service a request from other channel: channel-

specific registers, flags and parameter base address are automatically loaded for

the next serviced channel

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