SPC564A80L7 datasheet(16/157 Pages) STMICROELECTRONICS

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Introduction

SPC564A74L7, SPC564A80B4, SPC564A80L7

16/157

Doc ID 15399 Rev 9

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An access protection error is detected if a memory reference does not hit in any

memory region or the reference is flagged as illegal in all memory regions where it

does hit. In the event of an access error, the XBAR reference is terminated with an

error response and the MPU inhibits the bus cycle being sent to the targeted slave

device

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64-bit error registers, one for each XBAR slave port, capture the last faulting

address, attributes, and detail information

1.5.6

FMPLL

The FMPLL allows the user to generate high speed system clocks from a 4 MHz to 40 MHz

crystal oscillator or external clock generator. Further, the FMPLL supports programmable

frequency modulation of the system clock. The PLL multiplication factor, output clock divider

ratio are all software configurable. The PLL has the following major features:

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Input clock frequency from 4 MHz to 40 MHz

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Reduced frequency divider (RFD) for reduced frequency operation without forcing the

PLL to relock

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Three modes of operation

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Bypass mode with PLL off

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Bypass mode with PLL running (default mode out of reset)

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PLL normal mode

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Each of the three modes may be run with a crystal oscillator or an external clock

reference

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Programmable frequency modulation

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Modulation enabled/disabled through software

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Triangle wave modulation up to 100 kHz modulation frequency

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Programmable modulation depth (0% to 2% modulation depth)

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Programmable modulation frequency dependent on reference frequency

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Lock detect circuitry reports when the PLL has achieved frequency lock and

continuously monitors lock status to report loss of lock conditions

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Clock Quality Module

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Detects the quality of the crystal clock and causes interrupt request or system

reset if error is detected

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Detects the quality of the PLL output clock; if error detected, causes system reset

or switches system clock to crystal clock and causes interrupt request

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Programmable interrupt request or system reset on loss of lock

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Self-clocked mode (SCM) operation

1.5.7

SIU

The SPC564A80 SIU controls MCU reset configuration, pad configuration, external

interrupt, general purpose I/O (GPIO), internal peripheral multiplexing, and the system reset

operation. The reset configuration block contains the external pin boot configuration logic.

The pad configuration block controls the static electrical characteristics of I/O pins. The

EBI not available on all packages and is not available, as a master, for customer.

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