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LSM6DSO Datasheet(PDF) 47 Page - STMicroelectronics |
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LSM6DSO Datasheet(HTML) 47 Page - STMicroelectronics |
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47 / 172 page ![]() 9.7 COUNTER_BDR_REG1 (0Bh) Counter batch data rate register 1 (r/w) Table 33. COUNTER_BDR_REG1 register dataready_ pulsed RST_ COUNTER _BDR TRIG_ COUNTER _BDR 0 0 CNT_BDR_ TH_10 CNT_BDR_ TH_9 CNT_BDR_ TH_8 Table 34. COUNTER_BDR_REG1 register description dataready_pulsed Enables pulsed data-ready mode (0: Data-ready latched mode (returns to 0 only after an interface reading) (default); 1: Data-ready pulsed mode (the data ready pulses are 75 µs long) RST_COUNTER_BDR Resets the internal counter of batching events for a single sensor. This bit is automatically reset to zero if it was set to ‘1’. TRIG_COUNTER_BDR Selects the trigger for the internal counter of batching events between XL and gyro. (0: XL batching event; 1: GYRO batching event) CNT_BDR_TH_[10:8] In conjunction with CNT_BDR_TH_[7:0] in COUNTER_BDR_REG2 (0Ch), sets the threshold for the internal counter of batching events. When this counter reaches the threshold, the counter is reset and the COUNTER_BDR_IA flag in FIFO_STATUS2 (3Bh) is set to ‘1’. LSM6DSO COUNTER_BDR_REG1 (0Bh) DS12140 - Rev 2 page 47/172 |
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