LSM6DSO datasheet(71/172 Pages) STMICROELECTRONICS

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9.38

FIFO_STATUS1 (3Ah)

FIFO status register 1 (r)

Table 111. FIFO_STATUS1 register

DIFF_

FIFO_7

DIFF_

FIFO_6

DIFF_

FIFO_5

DIFF_

FIFO_4

DIFF_

FIFO_3

DIFF_

FIFO_2

DIFF_

FIFO_1

DIFF_

FIFO_0

Table 112. FIFO_STATUS1 register description

DIFF_FIFO_[7:0]

Number of unread sensor data (TAG + 6 bytes) stored in FIFO

In conjunction with DIFF_FIFO[9:8] in FIFO_STATUS2 (3Bh).

9.39

FIFO_STATUS2 (3Bh)

FIFO status register 2 (r)

Table 113. FIFO_STATUS2 register

FIFO_

WTM_IA

FIFO_

OVR_IA

FIFO_

FULL_IA

COUNTER

_BDR_IA

FIFO_OVR_

LATCHED

0(1)

DIFF_

FIFO_9

DIFF_

FIFO_8

1. This bit must be set to '0' for the correct operation of the device.

Table 114. FIFO_STATUS2 register description

FIFO_

WTM_IA

FIFO watermark status. Default value: 0

(0: FIFO filling is lower than WTM;

1: FIFO filling is equal to or greater than WTM)

Watermark is set through bits WTM[8:0] in FIFO_CTRL2 (08h) and FIFO_CTRL1 (07h).

FIFO_

OVR_IA

FIFO overrun status. Default value: 0

(0: FIFO is not completely filled; 1: FIFO is completely filled)

FIFO_

FULL_IA

Smart FIFO full status. Default value: 0

(0: FIFO is not full; 1: FIFO will be full at the next ODR)

COUNTER_

BDR_IA

Counter BDR reaches the CNT_BDR_TH_[10:0] threshold set in COUNTER_BDR_REG1 (0Bh) and

COUNTER_BDR_REG2 (0Ch). Default value: 0

This bit is reset when these registers are read.

FIFO_OVR_

LATCHED

Latched FIFO overrun status. Default value: 0

This bit is reset when this register is read.

DIFF_

FIFO_[9:8]

Number of unread sensor data (TAG + 6 bytes) stored in FIFO. Default value: 00

In conjunction with DIFF_FIFO[7:0] in FIFO_STATUS1 (3Ah)

LSM6DSO

FIFO_STATUS1 (3Ah)

DS12140 - Rev 2

page 71/172

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