D950-CORE datasheet(26/89 Pages) STMICROELECTRONICS

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D950-Core

4.3.2 Registers

Data registers

•

LS0 / LS1 / LS2: 3 x 16-bit Loop Start address registers,

•

LE0 / LE1 / LE2: 3 x 16-bit Loop End address registers,

•

LC0 / LC1 / LC2: 3 x 16-bit Loop Count registers.

All these registers are addressed directly by the LSP instruction (see Section 4.3.5)

After reset, LSP = 0. (No hardware loop is selected).

Control registers

•

STA: Bits 14 and 15 are dedicated to PCU (see Section 4.5.1).

•

CCR: Bits 14 and 15 are dedicated to PCU (see Section 4.5.2).

4.3.3 Instruction pipeline

Instruction execution is performed in a 3-stage pipeline: fetch/decode/execute. While

instruction n is executed, instruction n+1 is decoded and instruction n+2 is fetched.

The instruction cycle period is twice the CLKIN period.

According to the number of words used, D950-Core instructions can be of two types

•

One word instruction: Inside this group, most D950-Core instructions are one

cycle instructions (all arithmetic and logic instructions except instructions

performing double precision multiplication and bit manipulations). Some

instructions are multiple cycle instructions. Instructions causing a program flow

change (JUMP, CALL, RTS, RTI, SWI, RESET, BREAK, CONTINUE) are

executed in two or three cycles.

•

Instructions with extension words: As one program memory word is fetched

at each cycle, if an instruction needs extension words, they are fetched during

the cycles following the first fetch.

4.3.4 Interrupt Sources

The D950-Core includes three interrupt sources. The following table orders the interrupt

sources from highest to lowest priority

D950-CORE Datasheet(PDF) 26 Page - STMicroelectronics