AT697F datasheet(74/155 Pages) ATMEL

74 / 155 page

7703C–AERO–6/09

AT697F ADVANCE INFORMATION

The PLL implemented is configured by hardware to provide a cpu clock frequency four times the

frequency of the input clock.

PLL control

The PLL control is done by hardware through dedicated ports, including a bypass, a clock input

and a filter input.

The following table presents the assignement and functions of the PLL control signals.

Table 27. PLL ports description

Pin name

Function

LOCK

Lock

CLK

Board clock input

BYPASS

Bypass

Operation

To drive the device from the internal PLL, the CLK input shall be driven by an external clock gen-

erator while the BYPASS pin is driven low. In that way, the CPU clock frequency is four time the

frequency of the clock applied to CLK.

When the PLL based CPU clock source is selected, the clock input shall be driven at a fre-

quency in the range of 18MHz up to 25MHz.

Fault Tolerance &

Clock

To prevent erroneous operations from single event transient (SET) errors and single event upset

(SEU), the AT697F processor is based on full triple modular redundancy (TMR) architecture.

Figure 48. TMR structure

Such architecture is based on a fully triplicated clock distribution (CLK1, CLK2 and CLK3). In

that way, each one of the PCI clock and the cpu clock are build as three-clock trees.

Skew

To prevent the processor from corruption by single event transient (SET) phenomenon, addi-

tional skew can be programmed on the clock trees. The two dedicated pins SKEW1 and SKEW0

are used to program the delay induced by the skew.

Here is a short description of the skew implementation :

AT697F Datasheet(PDF) 74 Page - ATMEL Corporation