AT697F datasheet(36/155 Pages) ATMEL

36 / 155 page

7703C–AERO–6/09

AT697F ADVANCE INFORMATION

during a PROM read access. Setting MCFG1

PRWWS defines the number of waitstates to

insert during a PROM write.

MCFG1 PRRWS and MCFG1 PRWWS can be programmed to take values from 0 up to 15.

The effective number of waitstates applied during an access is then twice the programmed

value. In that way, programming two waitstates results in the insertion of four wait cycles during

the access.

Figure 20. ROM read access with PRRWS=1 (two programmed waitstate

data2

waitstate

lead-out

CLK

ROMS*

OE*

data1

waitstate

If the application needs more time for ROM transfer, it is possible to introduce more delay by

activating the hardware bus ready MCFG1 PBRDY. Refer to paragraph “BRDY Wait states”,

page 38.

After a reset operation of the processor (or at power up), the MCFG1

PRRWS and

MCFG1 PRWWS waitstates for the PROM area are set default to 15, resulting in 30 effective

waitstates and the MCFG1 PBRDY is set to 0.

Write Protection

Write protection is provided to prevent accidental over-writing to PROM area. It is controlled

through the PROM write enable bit MCFG1

PRWE. When set 1, this bit enables write to

PROM. When set 0, no PROM write transaction is available.

Bus width

To support applications with low memory and performance requirements, the PROM area can

be configured for 8-bit operations. The configuration of PROM in 8-bit mode is done program-

ming MCFG1 PRWDH.

When the PROM bus is configured as an 8-bit wide bus, data 31 downto 24 shall be used as

interface.

Figure 21.

PROM

OE*

AT697F

A[27:0]

D[31:24]

A[27:0]

WRITE*

ROMS0*

PROM 8-bit bus width connection

Since access to memory is always done on 32-bit word basis, read access to 8-bit memory will

be transformed in a burst of four read transactions. If EDAC protection is active, 5 read cycles

are necessary to complete the access (please refer to protection section for more details). Dur-

ing write operation, only the necessary bytes are writen.

Access Error

An access error can be indicated to the processor asserting the BEXC* signal. If enabled by set-

ting logical one to MCFG1 BEXC , the BEXC* signal is sampled with the data.

•

Trap 0x01 is taken if an instruction fetch is in progress

•

Trap 0x09 is taken if a data space is in progress

AT697F Datasheet(PDF) 36 Page - ATMEL Corporation

AT697F Datasheet(HTML) 36 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL