AT697F datasheet(14/155 Pages) ATMEL

14 / 155 page

7703C–AERO–6/09

AT697F ADVANCE INFORMATION

PCI_CLK provides timing for all transactions on PCI. All other PCI signals, except RST*, are

sampled on the rising edge of PCI_CLK and all other timing parameters are defined with respect

to this edge.

RST* - PCI Reset (input)

Reset is used to bring PCI-specific registers, sequencers, and signals to a consistent state.

PERR* - Parity Error (bi-directional)

Parity Error is only for the reporting of data parity errors during all PCI transactions except a

Special Cycle. The PERR* pin is sustained tri-state and must be driven active by the agent

receiving data two clocks following the data when a data parity error is detected. The minimum

duration of PERR* is one clock for each data phase that a data parity error is detected.

SERR* - System Error (bi-directional)

System Error is for reporting address parity errors, data parity errors on the special cycle com-

mand, or any other system error where the result will be catastrophic. If an agent does not want

a non-maskable interrupt (NMI) to be generated, a different reporting mechanism is required.

SYSEN* - PCI Host (input)

This active low input specifies the configuration of the device. At boot-up time, if SYSEN* is sam-

pled at a low level, the device is configured as the host of the PCI bus. If SYSEN* is sampled at

a high level, the device is configured as a satellite.

AT697F Datasheet(PDF) 14 Page - ATMEL Corporation