AT697F datasheet(53/155 Pages) ATMEL

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AT697F ADVANCE INFORMATION

7703C–AERO–6/09

Initiator Mapping

For standard operation, the PCI interface only works in a limited address range. The address

range for such initiator transaction is limited to addresses between 0xA0000000 and

0xF0000000.

PCI addresses outside of this predefined range can be accessed only via DMA transactions.

Instructions of different width (byte, half-word, word, double) can be performed for each address

of the PCI address range. The three low significant bits of the address A[2:0] are used to deter-

mine which PCI byte enable line C/BE*[3:0] should be active during the transaction.

According to the SPARC architecture, big-endian mapping is implemented, the most significant

byte standing at the lower address (0x..00) and the least significant byte standing to the upper

address (0x..03).

A byte-writing to A[1:0] = 00 results in the byte enable pattern 0111, indicating that the e most

significant byte lane (bits 31:24) of the PCI data bus is selected.

The following table presents the transaction width authorized for PCI transfers.

Table 20. Byte Enable Settings

width

Assembler

ld[s/u]b, stb

ld[s/u]h, sth

ld, st

ldd, std

C-datatype

char

short

int

long long

A[2:0]=000

0111

0011

0000

0000 (burst)

A[2:0]=100

0111

0011

0000

not aligned

A[2:0]=x01

1011

not aligned

A[2:0]=x10

1101

1100

not aligned

A[2:0]=x11

1110

not aligned

Note:

PCI byte enables are active low.

For non-aligned accesses, the byte enable pattern (1111) is issued on PCI, to avoid destroying

data in the remote PCI target.

Memory cycles

Many memory transactions such as memory-read/write and memory-read-line/write-invalidate

can be issued from the processor with common SPARC instruction set. Selection of the com-

mand to execute is performed setting the value PCIIC COMMSB.

Setting logical ‘01’ in PCIIC COMMSB result in the generation of memory read/write access

when PCI address is accessed. A logical value of ‘10’ result in a memory read line or write and

invalidate on PCI address access.

For the memory commands the address issued on the PCI bus is a word address with bits (1:0)

set to 00. This indicates that the linear incrementing mode is used.

operation

The following procedure shall be used to engage memory transaction on the PCI interface:

Select the initiator mode by setting logical one in the PCIIC MOD.

Select the memory load/store command or the memory read-line/write and invalidate

command in the PCI initiator configuration register. The PCIIC COMMSB shall be set

logical ‘01’ for simple load/store operation and shall be set logical ’11’ for read-line/write-

&-invalidate.

Enabling the interrupt signalisation is optionnal. It can be enabled setting logical one in

PCIITE IMIER. Up to four interrupt sources can be defined : Initiator Error, Initiator Par-

ity Error, PCI core error and system error.

Engage an access to a memory address mapped in the PCI address range.

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