AT697F datasheet(62/155 Pages) ATMEL

62 / 155 page

7703C–AERO–6/09

AT697F ADVANCE INFORMATION

Table 21. Trace buffer data allocation, Instruction tracing mode

Bits

Name

Definition

127

Instruction breakpoint hit

Set to ‘1’ if a DSU instruction breakpoint hit occurred.

126

Multi-cycle instruction

Set to ‘1’ on the second and third instance of a multi-cycle

instruction (LDD, ST or FPOP)

125:96

DSU counter

The value of the DSU counter

95:64

Load/Store parameters

Instruction result, Store address or Store data

63:34

Program counter

Program counter (2 lsb bits removed since they are always

zero)

Instruction trap

Set to ‘1’ if traced instruction trapped

Processor error mode

Set to ‘1’ if the traced instruction caused processor error mode

31:0

Opcode

Instruction opcode

When a trace is frozen, interrupt 11 is generated.

Bus Trace

The bus trace mode is enabled setting logical one the trace instruction enable bit TBC TA.

During bus tracing, one operation of the internal bus is stored per line in the trace buffer.

Table 22.

Bits

Name

Definition

127

AHB breakpoint hit

Set to ‘1’ if a DSU AHB breakpoint hit occurred.

126

Unused

125:96 DSU counter

The value of the DSU counter

95:92

IRL

Processor interrupt request input

91:88

PIL

Processor interrupt level (psr.pil)

95:80

Trap type

Processor trap type (psr.tt)

Hwrite

AHB HWRITE

78:77

Htrans

AHB HTRANS

76:74

Hsize

AHB HSIZE

73:71

Hburst

AHB HBURST

70:67

Hmaster

AHB HMASTER

Hmastlock

AHB HMASTLOCK

65:64

Hresp

AHB HRESP

63:32

Load/Store data

AHB HRDATA or HWDATA

31:0

Load/Store address

AHB HADDR

Trace Buffer Data Allocation, Internal bus Tracing Mode

Mixed Trace

In mixed mode, the buffer is divided on two halves, with instructions stored in the lower half and

bus transfers in the upper half. The MSB bit of the AHB index counter is then automatically kept

high, while the MSB of the instruction index counter is kept low.

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