AT697F datasheet(84/155 Pages) ATMEL

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7703C–AERO–6/09

AT697F ADVANCE INFORMATION

Floating Point Condition

Code

Table 42.

FCC

Description

f rs1 = f rs2

f rs1 < f rs2

f rs1 > f rs2

f rs1 ? f rs2

indicates an unordered relation, which is true if either

f rs1 or f rs2 is a signaling NaN or quiet NaN

FCC Field Definition

Note:

f rs1 and f rs2 correspond to the single, double, or quad values in the f registers specified by an

instruction’s rs1 and rs2 fields. Note that fcc is unchanged if FCMP or FCMPE generates an

IEEE_exception trap.

Floating Point Exception

Fields

The current and accrued exception fields and the trap enable mask assume the following defini-

tions of the floating-point exception conditions.

Table 43. Exception Fields

Aexc

Mnemonic

Cexc

Mnemonic

Name

Description

nva

nvc

Invalid

An operand is improper for the operation to be performed. 1 = invalid operand, 0 = valid operand(s).

Examples : 0

÷ 0, ∞ − ∞ are invalid.

ofa

ofc

Overflow

The rounded result would be larger in magnitude than the largest normalized number in the specified format. 1 =

overflow, 0 = no overflow.

ufa

ufc

Underflow

The rounded result is inexact and would be smaller in magnitude than the smallest normalized number in the

indicated format. 1 = underflow, 0 = no underflow. Underflow is never indicated when the correct unrounded

result is zero.

if UFM=0 : The ufc and ufa bits will be set if the correct unrounded result of an operation is less in magnitude than

the smallest normalized number and the correctly-rounded result is inexact. These bits will be set if the correct

unrounded result is less than the smallest normalized number, but the correct rounded result is the smallest

normalized number. nxc and nxa are always set as well.

if UFM=1 : An IEEE_exception trap will occur if the correct unrounded result of an operation would be smaller

than the smallest normalized number. A trap will occur if the correct unrounded result would be smaller than the

smallest normalized number, but the correct rounded result would be the smallest normalized number.

dza

dzc

Div_by_zero

÷0, where X is subnormal or normalized.

Note that 0

÷ 0 does not set the dzc bit.

1 = division-by-zero, 0 = no division-by-zero.

nxa

nxc

Inexact

The rounded result of an operation differs from the infinitely precise correct result.

1 = inexact result, 0 = exact result.

Table 44. f registers - fx ( 0 < x < 31)

fx[31:0]

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