AT697F datasheet(57/155 Pages) ATMEL

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AT697F ADVANCE INFORMATION

7703C–AERO–6/09

UARTs (UART1

and UART2)

The Universal Asynchronous Receiver and Transmitter (UART) is a highly flexible serial commu-

nication module. The AT697 implements two uarts : UART1 and UART2. Uarts on the processor

are defined as alternate functions of the general purpose interface (GPI).

Overview

The two UART’s provide double buffering. Each UART consists of a transmitter holding register,

a receiver holding register, a transmitter shift register, and a receiver shift register. Each of these

registers are 8-bit wide.

Figure 36. UART Block Diagram

CTS

RTS

Baud-rate

generator

Receiver Shift Register

Receiver Holding Register

Transmitter Shift Register

Transmitter Holding Register

Uart Status Reg.

UASn

Uart Scaler Reg.

UASCAn

Uart Data Reg.

Uart Control Reg.

UADn

UACn

control logic

Each UART is fully controlled by a set of four registers including :

•

a control register

•

a status register

•

a scaler register

•

and a data register

Serial Frame

A serial frame is defined to be one character of data bits with synchronisation bits (start and stop

bits), and optionnaly a parity bit for error checking.

Frame formats

Two frame formats are accepted by the AT697 UARTs, the only difference being the presence

or the absence of the parity bit. All the frames are built on an eight data bits basis.

A frame starts with the synchronization start bit followed by the least significant data bit. Then

the next data bits, up to a total of eight, are succeeding, ending with the most significant bit. If

enabled by setting the UACx PEx, the parity bit is inserted after the data bits and before the

stop bit.

The following figure illustrates the accepted frame formats.

Figure 37. Data frame format

Start D0

Stop

Start D0

Stop

Parity

Data frame, no parity:

Data frame with parity:

Parity bit

The parity bit is calculated by doing an exclusive-or of all the data bits. The odd parity is configured set-

ting logical one the UACx

PSx . In this case, the result of the exclusive or is inverted. An even parity can

be selected setting logical zero the UACx PSx.

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