AT697F datasheet(35/155 Pages) ATMEL

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AT697F ADVANCE INFORMATION

7703C–AERO–6/09

PROM Interface

Overview

The memory controller give the capability to control up to 512Mbyte of PROM. The PROM inter-

face can manage up to two PROM banks. The control of the PROM memory accesses uses a

standard set of pin, including chip selects (ROMS*x), output enable (OE*), read (READ) and

write (WRITE*) lines.

The bank size of the PROM banks is not programmable. The lower half part of the PROM area

(0x00000000 up to 0x0FFFFFFF) is controlled by the ROMS0* PROM select signal. The upper

half part of the PROM area (0x10000000 up to 0x1FFFFFFF) is controlled by the ROMS1*

PROM select signal.

PROM Read Access

A read access to PROM consists in two data cycles and waitstates if any programmed. On non-

consecutive accesses, a lead-out cycle is added after a read transaction to prevent bus conten-

tion due to slow turn-off time of memories or I/O devices. On consecutive accesses, no lead-out

cycle is performed between the acesses but only one is performed at the end of the operations.

Figure 18. PROM Read transaction (0 Waitstate)

data1

data2

lead-out

CLK

ROMS*

OE*

PROM Write Access

Each write access to PROM consists of three states and of waitstates if any programmed. The

three mandatory states are divided in one write setup cycle, one data cycle and one lead-out

cycle. The write operation is strobed by the WRITE* signal.

Figure 19. PROM Write transaction (0 waitstate)

lead-in

data

lead-out

CLK

ROMS*

WRITE*

Waitstates

For application using slow ROM memories, the ROM controller provides the capability to insert

wait-states during the accesses. Two types of wait-states can be inserted :

•

Programmed delay

•

‘Hardware’ bus ready delay

Up to 30 waitstates can be programmed for PROM accesses. Read and write waitstates can be

individually programmed. Setting MCFG1 PRRWS defines the number of waitstates to insert

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