ATtiny88 datasheet(64/266 Pages) ATMEL

64 / 266 page

8008C–AVR–03/09

ATtiny48/88

10.3.2

Alternate Functions of Port B

The Port B pins with alternate functions are shown in Table 10-5.

The alternate pin configuration is as follows:

• PCINT7 – Port B, Bit 7

PCINT7: Pin Change Interrupt source 7. The PB7 pin can serve as an external interrupt source.

If PB7 is used as a clock pin, DDB7, PORTB7 and PINB7 will all read 0.

• CLKI/PCINT6 – Port B, Bit 6

CLKI: External clock input. When used as a clock pin, the pin can not be used as an I/O pin.

PCINT6: Pin Change Interrupt source 6. The PB6 pin can serve as an external interrupt source.

If PB6 is used as a clock pin, DDB6, PORTB6 and PINB6 will all read 0.

• SCK/PCINT5 – Port B, Bit 5

SCK: Master Clock output, Slave Clock input pin for SPI channel. When the SPI is enabled as a

Slave, this pin is configured as an input regardless of the setting of DDB5. When the SPI is

enabled as a Master, the data direction of this pin is controlled by DDB5. When the pin is forced

by the SPI to be an input, the pull-up can still be controlled by the PORTB5 bit.

PCINT5: Pin Change Interrupt source 5. The PB5 pin can serve as an external interrupt source.

• MISO/PCINT4 – Port B, Bit 4

MISO: Master Data input, Slave Data output pin for SPI channel. When the SPI is enabled as a

Master, this pin is configured as an input regardless of the setting of DDB4. When the SPI is

enabled as a Slave, the data direction of this pin is controlled by DDB4. When the pin is forced

by the SPI to be an input, the pull-up can still be controlled by the PORTB4 bit.

Table 10-5.

Port B Pins Alternate Functions

Port Pin

Alternate Functions

PB7

PCINT7 (Pin Change Interrupt 7)

PB6

CLKI (

External clock input)

PCINT6 (Pin Change Interrupt 6)

PB5

SCK (SPI Bus Master clock Input)

PCINT5 (Pin Change Interrupt 5)

PB4

MISO (SPI Bus Master Input/Slave Output)

PCINT4 (Pin Change Interrupt 4)

PB3

MOSI (SPI Bus Master Output/Slave Input)

PCINT3 (Pin Change Interrupt 3)

PB2

SS (SPI Bus Master Slave select)

OC1B (Timer/Counter1 Output Compare Match B Output)

PCINT2 (Pin Change Interrupt 2)

PB1

OC1A (Timer/Counter1 Output Compare Match A Output)

PCINT1 (Pin Change Interrupt 1)

PB0

ICP1 (Timer/Counter1 Input Capture Input)

CLKO (Divided System Clock Output)

PCINT0 (Pin Change Interrupt 0)

ATtiny88 Datasheet(PDF) 64 Page - ATMEL Corporation

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