ATtiny88 datasheet(13/266 Pages) ATMEL

13 / 266 page

8008C–AVR–03/09

ATtiny48/88

4.7

Instruction Execution Timing

This section describes the general access timing concepts for instruction execution. The AVR

CPU is driven by the CPU clock clk

CPU, directly generated from the selected clock source for the

chip. No internal clock division is used.

Figure 4-4 shows the parallel instruction fetches and instruction executions enabled by the Har-

vard architecture and the fast-access Register File concept. This is the basic pipelining concept

to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,

functions per clocks, and functions per power-unit.

Figure 4-4.

The Parallel Instruction Fetches and Instruction Executions

Figure 4-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU

operation using two register operands is executed, and the result is stored back to the destina-

tion register.

Figure 4-5.

Single Cycle ALU Operation

4.8

Reset and Interrupt Handling

The AVR provides several different interrupt sources. These interrupts and the separate Reset

Vector each have a separate program vector in the program memory space. All interrupts are

assigned individual enable bits which must be written logic one together with the Global Interrupt

Enable bit in the Status Register in order to enable the interrupt. Depending on the Program

Counter value, interrupts may be automatically disabled when Lock Bits LB2 or LB1 are pro-

grammed. This feature improves software security. See the section “Memory Programming” on

page 184 for details.

The lowest addresses in the program memory space are by default defined as the Reset and

Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 47. The list also

determines the priority levels of the different interrupts. The lower the address the higher is the

clk

1st Instruction Fetch

1st Instruction Execute

2nd Instruction Fetch

2nd Instruction Execute

3rd Instruction Fetch

3rd Instruction Execute

4th Instruction Fetch

CPU

Total Execution Time

ALU Operation Execute

Result Write Back

clk

CPU

ATtiny88 Datasheet(PDF) 13 Page - ATMEL Corporation

ATtiny88 Datasheet(HTML) 13 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL