ATtiny88 datasheet(31/266 Pages) ATMEL

31 / 266 page

8008C–AVR–03/09

ATtiny48/88

Interrupts must be disabled when changing prescaler setting to make sure the write procedure is

not interrupted.

6.8

6.8.1

OSCCAL – Oscillator Calibration Register

The Oscillator Calibration Register is used to trim the internal oscillator to remove process varia-

tions from the oscillator frequency. A pre-programmed calibration value is automatically written

to this register during chip reset, giving the factory calibrated frequency as specified in Table 21-

1 on page 203. The application software can write to the OSCCAL register to change the oscilla-

tor frequency. The oscillator can be calibrated to frequencies as specified in Table 21-1 on page

203. Calibration outside the given range is not guaranteed.

Note that this oscillator is used to time EEPROM and Flash write accesses, and the write times

will be affected accordingly. If the EEPROM or Flash are written, do not calibrate to more than

8.8 MHz. Otherwise, the EEPROM or Flash write may fail.

All register bits are in use for frequency . A setting of 0x00 gives the lowest frequency and a set-

ting of 0xFF gives the highest frequency.

6.8.2

CLKPR – Clock Prescale Register

• Bit 7 – CLKPCE: Clock Prescaler Change Enable

The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE

bit is only updated when the other bits in CLKPR are simultaneously written to zero. CLKPCE is

cleared by hardware four cycles after it is written or when CLKPS bits are written. Rewriting the

CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the

CLKPCE bit.

• Bits 6..4 – Res: Reserved Bits

These bits are reserved and will always read zero.

• Bits 3..0 – CLKPS3..0: Clock Prescaler Select Bits 3 – 0

These bits define the division factor between the selected clock source and the internal system

clock. These bits can be written run-time to vary the clock frequency to suit the application

requirements. As the divider divides the master clock input to the MCU, the speed of all synchro-

nous peripherals is reduced when a division factor is used. The division factors are given in

Table 6-9.

The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed,

the CLKPS bits will be reset to 0b0000. If CKDIV8 is programmed, CLKPS bits are reset to

Bit

654

CAL7

CAL6

CAL5

CAL4

CAL3

CAL2

CAL1

CAL0

OSCCAL

Read/Write

R/W

Initial Value

Device Specific Calibration Value

Bit

3210

CLKPCE

–

CLKPS3

CLKPS2

CLKPS1

CLKPS0

CLKPR

Read/Write

R/W

Initial Value

See Bit Description

ATtiny88 Datasheet(PDF) 31 Page - ATMEL Corporation

ATtiny88 Datasheet(HTML) 31 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL