ATtiny88 datasheet(34/266 Pages) ATMEL

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8008C–AVR–03/09

ATtiny48/88

Idle mode enables the MCU to wake up from external triggered interrupts as well as internal

ones like the SPI interrupts. If wake-up from the Analog Comparator interrupt is not required, the

Analog Comparator can be powered down by setting the ACD bit in the Analog Comparator

Control and Status Register – ACSR. This will reduce power consumption in Idle mode. If the

ADC is enabled, a conversion starts automatically when this mode is entered.

7.1.2

ADC Noise Reduction Mode

When the SM1..0 bits are written to 01, the SLEEP instruction makes the MCU enter ADC Noise

Reduction mode, stopping the CPU but allowing the ADC, the external interrupts, the 2-wire

Serial Interface address watch and the Watchdog to continue operating (if enabled). This sleep

mode basically halts clk

I/O, clkCPU, and clkFLASH, while allowing the other clocks to run.

This improves the noise environment for the ADC, enabling higher resolution measurements. If

the ADC is enabled, a conversion starts automatically when this mode is entered. Apart from the

ADC Conversion Complete interrupt, only an External Reset, a Watchdog System Reset, a

Watchdog Interrupt, a Brown-out Reset, a 2-wire Serial Interface address match, an EEPROM

ready interrupt, an external level interrupt on INT0 or INT1 or a pin change interrupt can wake up

the MCU from ADC Noise Reduction mode.

7.1.3

Power-down Mode

When the SM1..0 bits are written to 10, the SLEEP instruction makes the MCU enter Power-

down mode. In this mode, the external oscillator is stopped, while the external interrupts, the 2-

wire Serial Interface address watch, and the Watchdog continue operating (if enabled). Only an

External Reset, a Watchdog System Reset, a Watchdog Interrupt, a Brown-out Reset, a 2-wire

Serial Interface address match, an external level interrupt on INT0 or INT1, or a pin change

interrupt can wake up the MCU. This sleep mode basically halts all generated clocks, allowing

operation of asynchronous modules only.

Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed

level must be held for some time to wake up the MCU. Refer to “External Interrupts” on page 48

for details.

When waking up from Power-down mode, there is a delay from the wake-up condition occurs

until the wake-up becomes effective. This allows the clock to restart and become stable after

having been stopped. The wake-up period is defined by the same CKSEL Fuses that define the

Reset Time-out period, as described in “Clock Sources” on page 26.

7.2

Software BOD Disable

When the Brown-out Detector (BOD) is enabled by BODLEVEL fuses (see Table 20-4 on page

185), the BOD is actively monitoring the power supply voltage during a sleep period. To save

power, it is possible for software to disable the BOD in Power-Down Mode. The sleep mode

power consumption will then be at the same level as when BOD is globally disabled by fuses. If

disabled by software, the BOD is turned off immediately after entering the sleep mode and auto-

matically turned on upon wake-up. This ensures safe operation in case the V

CC level has

dropped during the sleep period.

When the BOD has been disabled the wake-up time from sleep mode will be the same as the

wake-up time from RESET. This is in order to ensure the BOD is working correctly before the

MCU continues executing code.

BOD disable is controlled by bit 6, BODS (BOD Sleep) in the control register MCUCR, see

“MCUCR – MCU Control Register” on page 37. Writing this bit to one turns off the BOD in

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