ATtiny88 datasheet(75/266 Pages) ATMEL

75 / 266 page

8008C–AVR–03/09

ATtiny48/88

11. 8-bit Timer/Counter0

11.1

Features

• Two Independent Output Compare Units

• Clear Timer on Compare Match (Auto Reload)

• Three Independent Interrupt Sources (TOV0, OCF0A, and OCF0B)

11.2

Overview

Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independent Output

Compare Units. It allows accurate program execution timing (event management). A simplified

block diagram of the 8-bit Timer/Counter is shown in Figure 11-1. For the actual placement of

I/O pins, refer to “Pinout of ATtiny48/88” on page 2. CPU accessible I/O Registers, including I/O

bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed

in the “8-bit Timer/Counter Register Description” on page 80.

The PRTIM0 bit in “PRR – Power Reduction Register” on page 37 must be written to zero to

enable Timer/Counter0 module.

Figure 11-1. 8-bit Timer/Counter Block Diagram

11.2.1

Definitions

Many register and bit references in this section are written in general form, where a lower case

“n” replaces the Timer/Counter number (in this case 0) and a lower case “x” replaces the Output

Compare Unit (in this case Compare Unit A or Compare Unit B). However, when using the regis-

Clock Select

Timer/Counter

OCRnA

OCRnB

TCNTn

Fixed

TOP

Value

Control Logic

TOP

Count

Clear

TOVn

(Int.Req.)

OCnA (Int. Req.)

OCnB (Int. Req.)

TCCRnA

Edge

Detector

( From Prescaler )

clk

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