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WM8980CGEFL/V Datasheet(PDF) 62 Page - Wolfson Microelectronics plc |
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WM8980CGEFL/V Datasheet(HTML) 62 Page - Wolfson Microelectronics plc |
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62 / 123 page ![]() WM8980 Pre-Production w PP, Rev 3.8, May 2012 62 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R49 Output control 2 SPKBOOST 0 0 = speaker gain = -1; DC = AVDD / 2 1 = speaker gain = +1.5; DC = 1.5 x AVDD / 2 R1 Power management 1 8 BUFDCOPEN 0 Dedicated buffer for DC level shifting output stages when in 1.5x gain boost configuration. 0=Buffer disabled 1=Buffer enabled (required for 1.5x gain boost) Table 42 Speaker Boost Stage Control SPKBOOST OUTPUT STAGE GAIN OUTPUT DC LEVEL OUTPUT STAGE CONFIGURATION 0 1x (0dB) AVDD/2 Inverting 1 1.5x (3.52dB) 1.5xAVDD/2 Non-inverting Table 43 Output Boost Stage Details REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R43 Beep control 5 MUTERPGA2INV 0 Mute input to INVROUT2 mixer 4 INVROUT2 0 Invert ROUT2 output 3:1 BEEPVOL 000 AUXR input to ROUT2 inverter gain 000 = -15dB ... 111 = +6dB 0 BEEPEN 0 0 = mute AUXR beep input 1 = enable AUXR beep input Table 44 AUXR – ROUT2 BEEP Mixer Function |
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