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WM8980CGEFL/V Datasheet(PDF) 97 Page - Wolfson Microelectronics plc |
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WM8980CGEFL/V Datasheet(HTML) 97 Page - Wolfson Microelectronics plc |
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97 / 123 page  Pre-Production WM8980 w PP, Rev 3.8, May 2012 97 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 4 (04h) 8 BCP 0 BCLK polarity 0=normal 1=inverted Digital Audio Interfaces 7 LRP 0 right, left and i2s modes – LRCLK polarity 1 = invert LRCLK polarity 0 = normal LRCLK polarity Digital Audio Interfaces DSP Mode – mode A/B select 1 = MSB is available on 1st BCLK rising edge after LRC rising edge (mode B) 0 = MSB is available on 2nd BCLK rising edge after LRC rising edge (mode A) 6:5 WL 10 Word length 00=16 bits 01=20 bits 10=24 bits 11=32 bits Digital Audio Interfaces 4:3 FMT 10 Audio interface Data Format Select: 00=Right Justified 01=Left Justified 10=I 2S format 11= DSP/PCM mode Digital Audio Interfaces 2 DACLRSWAP 0 Controls whether DAC data appears in ‘right’ or ‘left’ phases of LRC clock: 0=DAC data appear in ‘left’ phase of LRC 1=DAC data appears in ‘right’ phase of LRC Digital Audio Interfaces 1 ADCLRSWAP 0 Controls whether ADC data appears in ‘right’ or ‘left’ phases of LRC clock: 0=ADC data appear in ‘left’ phase of LRC 1=ADC data appears in ‘right’ phase of LRC Digital Audio Interfaces 0 MONO 0 Selects between stereo and mono device operation: 0=Stereo device operation 1=Mono device operation. Data appears in ‘left’ phase of LRC Digital Audio Interfaces 5 (05h) 8:6 000 Reserved 5 WL8 0 Companding Control 8-bit mode 0=off 1=device operates in 8-bit mode Digital Audio Interfaces 4:3 DAC_COMP 00 DAC companding 00=off (linear mode) 01=reserved 10=µ-law 11=A-law Digital Audio Interfaces 2:1 ADC_COMP 00 ADC companding 00=off (linear mode) 01=reserved 10=µ-law 11=A-law Digital Audio Interfaces 0 LOOPBACK 0 Digital loopback function 0=No loopback 1=Loopback enabled, ADC data output is fed directly into DAC data input. Digital Audio Interfaces |
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