WM8980CGEFLSLASHV datasheet(31/123 Pages) WOLFSON

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Pre-Production

WM8980

PP, Rev 3.8, May 2012

ANALOGUE TO DIGITAL CONVERTER (ADC)

The WM8980 uses stereo multi-bit, oversampled sigma-delta ADCs. The use of multi-bit feedback

and high oversampling rates reduces the effects of jitter and high frequency noise. The ADC Full

Scale input level is proportional to AVDD. With a 3.3V supply voltage, the full scale level is 1.0Vrms.

Any voltage greater than full scale may overload the ADC and cause distortion.

ADC DIGITAL FILTERS

The ADC filters perform true 24 bit signal processing to convert the raw multi-bit oversampled data

from the ADC to the correct sampling frequency to be output on the digital audio interface. The digital

filter path for each ADC channel is illustrated in Figure 16.

Figure 16 ADC Digital Filter Path

The ADCs are enabled by the ADCENL/R register bit.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

Power

management 2

ADCENL

Enable ADC left channel:

0 = ADC disabled

1 = ADC enabled

ADCENR

Enable ADC right channel:

0 = ADC disabled

1 = ADC enabled

Table 12 ADC Enable Control

The polarity of the output signal can also be changed under software control using the

ADCLPOL/ADCRPOL register bit. The oversampling rate of the ADC can be adjusted using the

ADCOSR register bit. With ADCOSR=0 the oversample rate is 64x which gives lowest power

operation and when ADCOSR=1 the oversample rate is 128x which gives best performance.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R14

ADC Control

ADCLPOL

ADC left channel polarity adjust:

0=normal

1=inverted

ADCRPOL

ADC right channel polarity adjust:

0=normal

1=inverted

ADCOSR

ADC oversample rate select:

0=64x (lower power)

1=128x (best performance)

Table 13 ADC Control

WM8980CGEFL/V Datasheet(PDF) 31 Page - Wolfson Microelectronics plc

WM8980CGEFL/V Datasheet(HTML) 31 Page - Wolfson Microelectronics plc

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