WM8980CGEFLSLASHV datasheet(16/123 Pages) WOLFSON

16 / 123 page

WM8980

Pre-Production

PP, Rev 3.8, May 2012

Test Conditions

DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, TA=+25

oC, Master Mode, fs=48kHz,

MCLK=256fs, 24-bit data, unless otherwise stated.

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

Audio Data Input Timing Information

LRC propagation delay from BCLK falling edge

tDL

ADCDAT propagation delay from BCLK falling edge

tDDA

DACDAT setup time to BCLK rising edge

tDST

DACDAT hold time from BCLK rising edge

tDHT

AUDIO INTERFACE TIMING – SLAVE MODE

Figure 3 Digital Audio Data Timing – Slave Mode

Test Conditions

DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, TA=+25

oC, Slave Mode, fs=48kHz,

MCLK= 256fs, 24-bit data, unless otherwise stated.

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

Audio Data Input Timing Information

BCLK cycle time

tBCY

BCLK pulse width high

tBCH

BCLK pulse width low

tBCL

LRC set-up time to BCLK rising edge

tLRSU

LRC hold time from BCLK rising edge

tLRH

DACDAT hold time from BCLK rising edge

tDH

ADCDAT propagation delay from BCLK falling edge

tDD

Note:

BCLK period should always be greater than or equal to MCLK period.

WM8980CGEFL/V Datasheet(PDF) 16 Page - Wolfson Microelectronics plc

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