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WM8980CGEFL/V Datasheet(PDF) 19 Page - Wolfson Microelectronics plc |
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WM8980CGEFL/V Datasheet(HTML) 19 Page - Wolfson Microelectronics plc |
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19 / 123 page  Pre-Production WM8980 w PP, Rev 3.8, May 2012 19 INTERNAL POWER ON RESET CIRCUIT Figure 6 Internal Power on Reset Circuit Schematic The WM8980 includes an internal Power-On-Reset Circuit, as shown in Figure 6, which is used reset the digital logic into a default state after power up. The POR circuit is powered from AVDD and monitors DVDD. It asserts PORB low if AVDD or DVDD is below a minimum threshold. Figure 7 Typical Power up Sequence where AVDD is Powered before DVDD Figure 7 shows a typical power-up sequence where AVDD comes up first. When AVDD goes above the minimum threshold, Vpora, there is enough voltage for the circuit to guarantee PORB is asserted low and the chip is held in reset. In this condition, all writes to the control interface are ignored. Now AVDD is at full supply level. Next DVDD rises to Vpord_on and PORB is released high and all registers are in their default state and writes to the control interface may take place. On power down, where AVDD falls first, PORB is asserted low whenever AVDD drops below the minimum threshold Vpora_off. |
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