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WM8980CGEFL/V Datasheet(PDF) 69 Page - Wolfson Microelectronics plc |
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WM8980CGEFL/V Datasheet(HTML) 69 Page - Wolfson Microelectronics plc |
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69 / 123 page ![]() Pre-Production WM8980 w PP, Rev 3.8, May 2012 69 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R49 0 VROI 0 VREF (AVDD/2 or 1.5xAVDD/2) to analogue output resistance 0: approx 1k 1: approx 30 k Table 52 Disabled Outputs to VREF Resistance A dedicated buffer is available for tying off unused analogue I/O pins as shown in Figure 35. This buffer can be enabled using the BUFIOEN register bit. If the SPKBOOST, OUT3BOOST or OUT4BOOST bits are set, then the relevant outputs will be tied to the output of the DC level shift buffer at 1.5xAVDD/2 when disabled. Figure 35 summarises the tie-off options for the speaker and mono output pins. Figure 35 Unused Input/Output Pin Tie-off Buffers |
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