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WM8980CGEFL/V Datasheet(PDF) 108 Page - Wolfson Microelectronics plc |
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WM8980CGEFL/V Datasheet(HTML) 108 Page - Wolfson Microelectronics plc |
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108 / 123 page  WM8980 Pre-Production w PP, Rev 3.8, May 2012 108 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 5:0 INPPGA VOLL 010000 Left channel input PGA volume 000000 = -12dB 000001 = -11.25db . 010000 = 0dB . 111111 = 35.25dB Input Signal Path 46 (2Eh) 8 INPPGA UPDATE N/A INPPGAVOLL and INPPGAVOLR volume do not update until a 1 is written to INPPGAUPDATE (in reg 45 or 46) Input Signal Path 7 INPPGA ZCR 0 Right channel input PGA zero cross enable: 0=Update gain when gain register changes 1=Update gain on 1 st zero cross after gain register write. Input Signal Path 6 INPPGA MUTER 0 Mute control for right channel input PGA: 0=Input PGA not muted, normal operation 1=Input PGA muted (and disconnected from the following input BOOST stage). Input Signal Path 5:0 INPPGA VOLR 010000 Right channel input PGA volume 000000 = -12dB 000001 = -11.25db . 010000 = 0dB . 111111 = +35.25dB Input Signal Path 47 (2Fh) 8 PGA BOOSTL 1 Boost enable for left channel input PGA: 0 = PGA output has +0dB gain through input BOOST stage. 1 = PGA output has +20dB gain through input BOOST stage. Input Signal Path 7 0 Reserved 6:4 L2_2 BOOSTVOL 000 Controls the L2 pin to the left channel input boost stage: 000=Path disabled (disconnected) 001=-12dB gain through boost stage 010=-9dB gain through boost stage … 111=+6dB gain through boost stage Input Signal Path 3 0 Reserved 2:0 AUXL2 BOOSTVOL 000 Controls the auxiliary amplifer to the left channel input boost stage: 000=Path disabled (disconnected) 001=-12dB gain through boost stage 010=-9dB gain through boost stage … 111=+6dB gain through boost stage Input Signal Path 48 (30h) 8 PGA BOOSTR 1 Boost enable for right channel input PGA: 0 = PGA output has +0dB gain through input BOOST stage. 1 = PGA output has +20dB gain through input BOOST stage. Input Signal Path 7 0 Reserved |
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