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AD-DPGIOZ Datasheet(PDF) 32 Page - Analog Devices |
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AD-DPGIOZ Datasheet(HTML) 32 Page - Analog Devices |
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32 / 61 page ![]() AD9961/AD9963 Data Sheet Rev. A | Page 32 of 60 Register Name Register Address Bit(s) Parameter Function 3:0 N[3:0] Sets DLL divide ratio (1 to 8) at the output of the DLL. 0000: not valid. 0001: 1. 0010: 2. … 0110: 6. 0111: not valid. 1000: 8. 1001: not valid. … 1111: not valid. DLL Control 1 0x72 7 DLL_Locked 1: DLL has locked to reference clock (read only). 6:5 DLLDIV[1:0] 00: DLL output is directly driven out. Divider is bypassed. 01: DLL output is directly driven out. Divider is bypassed. 10: DLL output is divided by 2. 11: DLL output is divided by 4. 4:0 M[4:0] Sets DLL multiplication factor (1 to 32). 00000: 1. 00001: 2. … 11111: 32. DLL Control 2 0x75 7:4 0 Set these bits to 0. 3 DLL_RESB Reset DLL. The DLL must be reset by a low to high transition on this bit each time the DLL configuration is changed or the reference frequency is changed. 2:0 0 Set these bits to 0. Aux ADC Config 0x77 7:6 CONV_TIME[1:0] Sets the number of AUXADCCLK cycles required to perform a conversion. and Conversion Start 00: 20 AUXADCCLK cycles. 01: 22 AUXADCCLK cycles. 10: 26 AUXADCCLK cycles. 11: 34 AUXADCCLK cycles. 5:3 Unused 2:0 AUXADC_CH[2:0] Selects analog input channel to the auxiliary ADC. 000: AUXIN1, Pin 72. 001: AUXIO2, Pin 71. 010: AUXIO3, Pin 70. 011: internal VPTAT voltage. 100: internal VCMLI voltage. 101: internal VCMLQ voltage. 110: RXCML voltage. 111: not connected. Any write to this register initiates an ADC conversion cycle. Aux ADC MSBs 0x78 7:0 AUXADC[11:4] This is the 8 MSBs of the most recent AUXADC conversion result. Aux ADC LSBs 0x79 7:4 AUXADC[3:0] This is the 4 LSBs of the most recent AUXADC conversion result. 3 CONV_COMPL 0: indicates that the request auxiliary ADC conversion is in progress. 1: indicates that the auxiliary ADC conversion result is valid. 2:0 CHAN_SEL[2:0] Indicates the actual auxiliary ADC input channel selected for the conversion. This should match the channel that was selected in the write to Register 0x77 that initiated the conversion. |
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