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AD-DPGIOZ Datasheet(PDF) 11 Page - Analog Devices |
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AD-DPGIOZ Datasheet(HTML) 11 Page - Analog Devices |
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11 / 61 page  Data Sheet AD9961/AD9963 Rev. A | Page 11 of 60 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 AUX33V AUXADCREF RXQP RXQN RXGND RXBIAS RX18V RX33V RX18VF RXCML RXGND RXIN RXIP LDO_EN RESET SCLK 17 CS 18 SDIO 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 DLLFILT DLL18V DVDD18 DRVDD TXD0 TXD1 TXD2 TXD3 TXD4 TXD5 TXD6 TXD7 TXD8 TXD9 TXD10 TXD11 TXIQ/TXnRX TXCLK NOTES 1. EXPOSED PAD MUST BE SOLDERED TO PCB. PIN 1 INDICATOR AD9963 (TOP VIEW) Figure 3. AD9963 Pin Configuration Table 9. AD9963 Pin Function Descriptions Pin No. Mnemonic Description 1 AUX33V Analog Supply for the Auxiliary ADC and Auxiliary DACs (3.3 V ± 10%, 1.8 V ± 10% If Auxiliary ADC Is Powered Down). 2 AUXADCREF Reference Output (or input) for Auxiliary ADC. 3, 4 RXQP, RXQN Differential ADC Q Inputs. Full-scale input voltage range is 1.56 V p-p differential. 5, 11 RXGND Receive Path Ground. 6 RXBIAS External Bias Resistor Connection. This voltage is nominally 0.5 V. A 10 kΩ resistor can be connected between this pin and analog ground to improve the Rx ADC full-scale accuracy. 7 RX18V Output of RX18V Voltage Regulator. 8 RX33V Input to RX18V and RX18VF Voltage Regulators (2.5 V to 3.3 V). If LDOs are not being used, short Pin 8 to Pin 7. 9 RX18VF Output of RX18VF Voltage Regulator. 10 RXCML ADC Common-Mode Voltage Output. 12, 13 RXIN, RXIP Differential ADC I Inputs. Full-scale input voltage range is 1.56 V p-p differential. 14 LDO_EN Control pin for LDOs (GND = Disable all LDOs, Float = Enable DVDD18 LDO Only, DRVDD = Enable All LDOs). 15 RESET Reset. Active low to reset the configuration registers to default values and reset device. 16 SCLK Clock Input for Serial Port. 17 CS Active Low Chip Select. 18 SDIO Bidirectional Data Line for Serial Port. 19, 34 DGND Digital Core Ground. 20, 33, 51 DRVDD Input/Output Pad Ring Supply Voltage (1.8 V to 3.3 V). 21 to 32 TRXD11 to TRXD0 ADC Output Data in Full Duplex Mode. ADC output data and DAC input data in half-duplex mode. 35 TRXIQ Output Signal Indicating from Which ADC the Output Data Is Sourced. 36 TRXCLK Qualifying Clock for the TRXD Bus. 37 TXCLK Qualifying Clock for the TXD Bus. It can be configured as either an input or output. 38 TXIQ/TXnRX Dual Function Pin. In half-duplex mode (TXnRX), this pin controls the direction of the TRX port. In full- duplex mode (TXIQ), this input signal indicates to which DAC, I or Q, the TxDAC Input Data is intended. 39 to 50 TXD11 to TXD0 TxDAC Input Data. 52 DVDD18 Digital Core 1.8 V Supply. 53 DLL18V Output of DLL18V Voltage Regulator. |
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