AD-DPGIOZ datasheet(31/61 Pages) AD

31 / 61 page

Data Sheet

AD9961/AD9963

Rev. A | Page 31 of 60

Address

Bit(s)

Parameter

Function

Clock Mode

0x66

TXI_DCLK

1: disables internal clock to I DAC.

TXQ_DCLK

1: disables internal clock to Q DAC.

Unused

RXI_DCLK

1: disables internal clock to I ADC.

RXQ_DCLK

1: disables internal clock to Q ADC.

DCS_BP

1: disables duty cycle stabilizer block.

1:0

ADCDIV[1:0]

00: selects divide by 1. Bypasses internal divider block for RXCLK.

01: selects divide by 1. Bypasses internal divider block for RXCLK.

10: selects divide by 2.

11: selects divide by 4.

I DAC Gain Ctrl 0

0x68

7:6

Unused

5:0

IGAIN1[5:0]

Linear in dB adjustment of the full-scale current of I DAC. Provides an

adjustment range of approximately ±6 dB in 0.25 dB steps. See Figure 57

for details.

I DAC Gain Ctrl 1

0x69

7:6

Unused

5:0

IGAIN2[5:0]

Linear adjustment of the full-scale current of I DAC. Provides an

adjustment range of approximately ±2.5% in 0.08% steps. See Figure 55

for details.

I DAC Gain Ctrl 2

0x6A

7:6

Unused

5:0

IRSET[5:0]

Linear adjustment of the full-scale current of I DAC. Provides an

adjustment range of approximately ±20% in 0.625% steps. See Figure 55

for details.

Q DAC Gain Ctrl 0

0x6B

7:6

Unused

5:0

QGAIN1[5:0]

Linear in dB adjustment of the full-scale current of Q DAC. Provides an

adjustment range of approximately ±6 dB in 0.25 dB steps. See Figure 56

for details.

Q DAC Gain Ctrl 1

0x6C

7:6

Unused

5:0

QGAIN2[5:0]

Linear adjustment of the full-scale current of Q DAC. Provides an

adjustment range of approximately ±2.5% in 0.08% steps. See Figure 57

for details.

Q DAC Gain Ctrl 2

0x6D

7:6

Unused

5:0

QRSET[5:0]

Linear adjustment of the full-scale current of Q DAC. Provides an

adjustment range of approximately ±20% in 0.625% steps. See Figure 55

for details.

REFIO Adjust

0x6E

7:6

Unused

5:0

REFIO_ADJ[5:0]

Adjusts the on-chip reference voltage and output at REFIO. The transmit

DAC full-scale currents and the auxiliary DAC full-scale voltages are

proportional to the REFIO voltage. The approximate REFIO output

voltage by code is:

000000: V

REF = 1.0 V.

000001: V

REF = 1.00625 V.

…

011111: V

REF = 1.19375 V.

100000: V

REF = 0.8 V.

100001: V

REF = 0.80625 V.

…

111111 : V

REF = 0.99375 V.

DLL Control 0

0x71

ADCCLKSEL

1: selects DLL output as the ADC sampling clock.

0: selects external clock as the ADC sampling clock.

DACCLKSEL

1: selects DLL output as the DAC sampling clock.

0: selects external clock as the DAC sampling clock.

Unused

DLL_REF_EN

1: enables the input reference clock to the DLL.

AD-DPGIOZ Datasheet(PDF) 31 Page - Analog Devices

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