AD-DPGIOZ datasheet(49/61 Pages) AD

49 / 61 page

Data Sheet

AD9961/AD9963

Rev. A | Page 49 of 60

TRXIQ

TRXD[11:0]

TRXCLK

tOD2

Figure 75. Rx Timing, I ADC Only, Bus Rate Clock Mode

TRXIQ

TRXD[11:0]

TRXCLK

tOD2

Figure 76. Rx Timing, Q ADC Only, Bus Rate Clock Mode

TRXIQ

TRXD[11:0]

TRXCLK

tOD2

Figure 77. Rx Timing, I ADC Only, DDR Clock Mode

TRXIQ

TRXD[11:0]

TRXCLK

tOD2

Figure 78. Rx Timing, Q ADC Only, DDR Clock Mode

In addition to the different timing modes listed in Figure 75 to

Figure 78, the input data can also be delivered from the device

in either unsigned binary or twos complement format. The

format type is chosen via the RX_BNRY configuration bit.

TX PORT OPERATION (FULL-DUPLEX MODE)

The Tx port operates with a qualifying clock that can be

configured as either an input or an output. The input data

(TXD[11:0]) must be accompanied by the TXIQ signal which

identifies to which transmit channel (I or Q) the data is

intended. By default, the data and TXIQ signals are latched by

the device on the rising edge of TXCLK. The timing diagram is

shown in Figure 79

TXIQ

TXD[11:0]

TXCLK

tSU

tHD

Figure 79. Tx Port Timing Diagram (Data Rate Clock Mode)

The setup and hold time requirements for the Tx port in data

rate clock mode are given in Table 24.

The input samples to the device are assembled to create a

quadrature pair of data. The data can be arranged in two

possible data pairing orders and with two possible data to TXIQ

signal phase relationships. This creates four possible timing

modes. The AD9961/AD9963 can be configured to accept data

in any of these four modes. The data pairing order is controlled

by the TX_IFIRST bit. The data to TXIQ phase relationship is

controlled by the TXIQ_HILO bit. The two programming

options produce the four timing diagrams shown in Figure 80.

TXIQ

TXD[11 :0]

TX_IFIRST = 1

TXIQ_HILO = 1

TX_IFIRST = 1

TXIQ_HILO = 0

TX_IFIRST = 0

TXIQ_HILO = 1

TX_IFIRST = 0

TXIQ_HILO = 0

Figure 80. Transmit Path Data Pairing Options

In addition to the different timing modes listed above, the input

data can also be accepted by the device in either unsigned

binary or twos complement format. The format type is chosen

via the TX_BNRY configuration bit.

AD-DPGIOZ Datasheet(PDF) 49 Page - Analog Devices

AD-DPGIOZ Datasheet(HTML) 49 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61

Datasheet Download

Link URL