AD-DPGIOZ datasheet(25/61 Pages) AD

25 / 61 page

Data Sheet

AD9961/AD9963

Rev. A | Page 25 of 60

Address

Bit(s)

Parameter

Function

SRRC_BP

1: bypass 2× SRRC interpolation filter (SRRC).

The filter chain is SRRC

→INT0→INT1.

If SRRC filter is enabled, the other two filters are enabled too.

TXCLK_EN

1: enables data clocks for transmit path.

RxNTx

0: in HD SPI pin mode, TRx port operates in Tx mode.

1: in HD SPI pin mode, TRx port operates in Rx mode.

Tx Data Interface

0x31

TX_SDR

0: chooses DDR clocking mode. Tx data is driven out on both edges of

the TXCLK signal.

1: chooses bus rate clocking mode. Tx data is driven out on one edge of

the TXCLK signal.

TXCKO_INV

This signal inverts the phase of the transmit path output clock signal.

0: does not invert TxCLK output.

1: inverts TxCLK output.

5:4

TXCLK_MD[1:0]

Controls the mode of the TXCLK pin. The TXCLK pin can be configured as

an input or an output. When configured as an output, it can have two

possible sources, the internal TXCLK signal or the DLL output signal.

00: disabled.

01: the TXCLK pin is configured as an input.

10: the TXCLK pin is configured as an output. The source signal is the

transmit path clock signal.

11: the TXCLK pin is configured as an output. The source signal is the DLL

output signal.

Note that the TXCLK signal may appear on either the TXCLK pin or the

TRXCLK pin, depending on the mode of the device. In Half-Duplex 1-

Clock mode, this signal is present on the TRXCLK pin when TX is active. In

Half-Duplex 2-Clock mode and Full-Duplex mode, this signal is present

on the TXCLK pin.

TXCKI_INV

Selects which edge of the TXCLK signal samples the transmit path data.

0: TXPCLK negative edge latches transmit path data.

1: TXPCLK positive edge latches transmit path data.

TXIQ_HILO

Data appears on the TXD bus sequentially but is loaded into the transmit

path in pairs. TXIQ_HILO selects how the TXIQ signal marks each data

pair.

0: each data pair is marked by TXIQ being low then high.

1: each data pair is marked by TXIQ being high then low.

TX_IFIRST

This bit sets the data pairing order of the I and Q samples on transmit

path.

0: selects that Q is first, followed by I.

1: selects that I is first, followed by Q.

TX_BNRY

This bit selects the data format of the transmit path data.

0: Tx binary.

1: Tx twos complement.

Rx Data Interface

0x32

RX_SDR

0: chooses DDR clocking mode. Rx data is driven out on both edges of

the TRXCLK signal.

1: chooses bus rate clocking mode. Rx data is driven out on one edge of

the TRXCLK signal.

Unused

5:4

RXCLK_MD[1:0]

This sets the way the internal RXCLK signal in the chip is driven.

00: disabled.

01: disabled.

10: RXCLK is driven by internal Rx path clock.

AD-DPGIOZ Datasheet(PDF) 25 Page - Analog Devices

AD-DPGIOZ Datasheet(HTML) 25 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61

Datasheet Download

Link URL