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AD-DPGIOZ Datasheet(PDF) 30 Page - Analog Devices |
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AD-DPGIOZ Datasheet(HTML) 30 Page - Analog Devices |
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30 / 61 page ![]() AD9961/AD9963 Data Sheet Rev. A | Page 30 of 60 Register Name Register Address Bit(s) Parameter Function 5 TXI_SLEEP 1: turns off IDAC output current. 4 TXQ_SLEEP 1: turns off QDAC output current. 3 CLK_PD 1: turns off clock receiver. This disables all clocks on the chip except for the serial port clock. 2 RXADC_PD 1: powers down main ADC clock and the bandgap reference voltage common to both receive ADCs. 1 RXQ_SLEEP 1: powers down the Q ADC core. 0 RXI_SLEEP 1: powers down the I ADC core. Power Down 1 0x61 7 Unused 6 DLL_LDO_PD 1: powers down LDO that supplies the DLL18V voltage rail. 5 DLLBIAS_PD 1: powers down bias sub-block inside DLL block. 4 CLK_LDO_PD 1: powers down LDO that supplies the CLK18V voltage rail. 3 RX_LDO_PD 1: powers down LDO that supplies the RX18V voltage rail. 2 RXF_LDO_PD 1: powers down LDO that supplies the RX18VF voltage rail. 1 AUXADC_PD 1: powers down AUXADC block. 0 AUX_REF_PD 1: powers down the auxiliary ADC voltage reference, allowing an external reference to be used. LDO Status 0x62 7 DLL_LDO_STAT 1: LDO to DLL block is on (read only). 6 CLK_LDO_STAT 1: LDO to CLOCK block is on (read only). 5 RX_LDO_STAT 1: LDO to ADC blocks is on (read only). 4 RXF_LDO_STAT 1: LDO to FLASH section of ADC is on (read only). 3 DIG_LDO_STAT 1: LDO to digital core is on (read only). 2 Unused 1 Unused 0 RSET_SEL 0: selects internal 10 kΩ to generate 1 V reference. 1: selects external RSET to generate voltage reference. Output Drive 0x63 7:6 TRXD_DRV Controls the drive strength of the TRXD[11:0] pins. 00: 4 mA output drive. 01: 8 mA output drive. 10: 12 mA output drive. 11: not valid. 5:4 TRXIQ_DRV Controls the drive strength of the TRXIQ pin. 00: 4 mA output drive. 01: 8 mA output drive. 10: 12 mA output drive. 11: not valid. 3:2 TRXCLK_DRV Controls the drive strength of the TRXCLK pin. 00: 4 mA output drive. 01: 8 mA output drive. 10: 12 mA output drive. 11: not valid. 1:0 TXCLK_DRV Controls the drive strength of the TXCLK pin. 00: 4 mA output drive. 01: 8 mA output drive. 10: 12 mA output drive. 11: not valid. |
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