Electronic Components Datasheet Search
  British  ▼
ALLDATASHEET.CO.UK

X  

V62/12615-01XE-R Datasheet(PDF) 17 Page - Texas Instruments

Click here to check the latest version.
Part # V62/12615-01XE-R
Description  DP83848-EP PHYTER??Military Temperature Single Port 10/100 Mbps Ethernet Physical Layer Transceiver
PDF  98 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

V62/12615-01XE-R Datasheet(HTML) 17 Page - Texas Instruments

Back Button V62/12615-01XE-R Datasheet HTML 13Page - Texas Instruments V62/12615-01XE-R Datasheet HTML 14Page - Texas Instruments V62/12615-01XE-R Datasheet HTML 15Page - Texas Instruments V62/12615-01XE-R Datasheet HTML 16Page - Texas Instruments V62/12615-01XE-R Datasheet HTML 17Page - Texas Instruments V62/12615-01XE-R Datasheet HTML 18Page - Texas Instruments V62/12615-01XE-R Datasheet HTML 19Page - Texas Instruments V62/12615-01XE-R Datasheet HTML 20Page - Texas Instruments V62/12615-01XE-R Datasheet HTML 21Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 17 / 98 page
background image
TX_CLK
TX_EN
TXD
PMD output pair
(J/K)
T2.6.1
IDLE
DATA
RX_CLK
RXD[3:0]
RX_DV
RX_ER
Valid data
T2.5.2
T2.5.1
T2.5.1
17
DP83848-EP
www.ti.com
SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019
Submit Documentation Feedback
Product Folder Links: DP83848-EP
Specifications
Copyright © 2012–2019, Texas Instruments Incorporated
4.7.5
100-Mbps MII Receive Timing
PARAMETER
DESCRIPTION
NOTES
MIN
TYP
MAX
UNIT
T2.5.1
RX_CLK high/low time
100-Mbps Normal mode
16
20
24
ns
T2.5.2
RX_CLK to RXD[3:0], RX_DV,
RX_ER delay
100-Mbps Normal mode
10
30
ns
(1)
For Normal mode, latency is determined by measuring the time from the first rising edge of TX_CLK occurring after the assertion of
TX_EN to the first bit of the “J” code group as output from the PMD Output Pair. 1 bit time = 10 ns in 100-Mbps mode.
Figure 4-6. 100-Mbps MII Receive Timing
4.7.6
100BASE-TX Transmit Packet Latency Timing
PARAMETER
DESCRIPTION
NOTES(1)
MIN
TYP
MAX
UNIT
T2.6.1
TX_CLK to PMD output pair latency 100-Mbps Normal mode
6
bits
Figure 4-7. 100BASE-TX Transmit Packet Latency Timing



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com