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V62/12615-01XE-R Datasheet(PDF) 23 Page - Texas Instruments |
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V62/12615-01XE-R Datasheet(HTML) 23 Page - Texas Instruments |
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23 / 98 page  TX_CLK TX_EN PWD output pair PMD output pair 0 0 T2.16.1 T2.16.2 1 1 TX_CLK TX_EN TXD PMD output pair T2.15.2 T2.15.1 23 DP83848-EP www.ti.com SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 Submit Documentation Feedback Product Folder Links: DP83848-EP Specifications Copyright © 2012–2019, Texas Instruments Incorporated 4.7.15 10BASE-T Transmit Timing (Start of Packet) PARAMETER DESCRIPTION NOTES MIN TYP MAX UNIT T2.15.1 Transmit output delay from the falling edge of TX_CLK 10-Mbps MII mode 3.5 bits T2.15.2 Transmit output delay from the rising edge of TX_CLK 10-Mbps Serial mode 3.5 bits Figure 4-16. 10BASE-T Transmit Timing (Start of Packet) 4.7.16 10BASE-T Transmit Timing (End of Packet) PARAMETER DESCRIPTION NOTES MIN TYP MAX UNIT T2.16.1 End of packet high time (with ‘0’ ending bit) 250 300 ns T2.16.2 End of packet high time (with ‘1’ ending bit) 250 300 ns Figure 4-17. 10BASE-T Transmit Timing (End of Packet) |
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