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V62/12615-01XE-R Datasheet(PDF) 22 Page - Texas Instruments |
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V62/12615-01XE-R Datasheet(HTML) 22 Page - Texas Instruments |
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22 / 98 page ![]() RX_CLK RXD[0] RX_DV Valid data T2.14.2 T2.14.1 T2.14.1 TX_CLK TXD[0] TX_EN Valid data T2.13.1 T2.13.2 T2.13.3 T2.13.4 22 DP83848-EP SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 www.ti.com Submit Documentation Feedback Product Folder Links: DP83848-EP Specifications Copyright © 2012–2019, Texas Instruments Incorporated 4.7.13 10-Mbps Serial Mode Transmit Timing PARAMETER DESCRIPTION NOTES MIN TYP MAX UNIT T2.13.1 TX_CLK high time 10-Mbps Serial mode 20 25 30 ns T2.13.2 TX_CLK low time 10-Mbps Serial mode 70 75 80 ns T2.13.3 TXD_0, TX_EN data setup to TX_CLK rise 10-Mbps Serial mode 24.70 ns T2.13.4 TXD_0, TX_EN data hold from TX_CLK rise 10-Mbps Serial mode 0 ns (1) RX_CLK may be held high for a longer period of time during transition between reference and recovered clocks. Minimum high and low times will not be violated. Figure 4-14. 10-Mbps Serial Mode Transmit Timing 4.7.14 10-Mbps Serial Mode Receive Timing PARAMETER DESCRIPTION NOTES(1) MIN TYP MAX UNIT T2.14.1 RX_CLK high/low time 35 50 65 ns T2.14.2 RX_CLK fall to RXD_0, RX_DV delay 10-Mbps Serial mode –10 10 ns Figure 4-15. 10-Mbps Serial Mode Receive Timing |
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