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V62/12615-01XE-R Datasheet(PDF) 41 Page - Texas Instruments

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Part # V62/12615-01XE-R
Description  DP83848-EP PHYTER??Military Temperature Single Port 10/100 Mbps Ethernet Physical Layer Transceiver
PDF  98 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

V62/12615-01XE-R Datasheet(HTML) 41 Page - Texas Instruments

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MDC
MDIO
(STA)
Idle
Start
Opcode
(Write)
PHY Address
(PHYAD = 0Ch)
Register Address
(00h = BMCR)
TA
Register Data
Idle
z
z
0
1
0
1
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
z
z
MDC
MDIO
(STA)
Idle
Start
Opcode
(Read)
PHY Address
(PHYAD = 0Ch)
Register Address
(00h = BMCR)
TA
Register Data
z
MDIO
(PHY)
z
z
Idle
z
z
z
z
0
1
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
41
DP83848-EP
www.ti.com
SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019
Submit Documentation Feedback
Product Folder Links: DP83848-EP
Detailed Description
Copyright © 2012–2019, Texas Instruments Incorporated
The Start code is indicated by a <01> pattern. This assures the MDIO line transitions from the default idle
line state.
Turnaround is defined as an idle bit time inserted between the Register Address field and the Data field.
To avoid contention during a read transaction, no device shall actively drive the MDIO signal during the
first bit of Turnaround. The addressed DP83848-EP drives the MDIO with a zero for the second bit of
turnaround and follows this with the required data. Figure 5-2 shows the timing relationship between MDC
and the MDIO as driven/received by the Station (STA) and the DP83848-EP (PHY) for a typical register
read access.
For write transactions, the station management entity writes data to the addressed DP83848-EP thus
eliminating the requirement for MDIO Turnaround. The Turnaround time is filled by the management entity
by inserting <10>. Figure 5-3 shows the timing relationship for a typical MII register write access.
Figure 5-2. Typical MDC/MDIO Read Operation
Figure 5-3. Typical MDC/MDIO Write Operation
5.4.3.3
Serial Management Preamble Suppression
The DP83848-EP supports a Preamble Suppression mode as indicated by a one in bit 6 of the Basic
Mode Status Register (BMSR, address 01h.) If the station management entity (i.e. MAC or other
management controller) determines that all PHYs in the system support Preamble Suppression by
returning a one in this bit, then the station management entity need not generate preamble for each
management transaction.
The
DP83848-EP
requires
a
single
initialization
sequence
of
32
bits
of
preamble
following
hardware/software reset. This requirement is generally met by the mandatory pullup resistor on MDIO in
conjunction with a continuous MDC, or the management access made to determine whether Preamble
Suppression is supported.
While the DP83848-EP requires an initial preamble sequence of 32 bits for management initialization, it
does not require a full 32-bit sequence between each subsequent transaction. A minimum of one idle bit
between management transactions is required as specified in the IEEE 802.3u specification.



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