V62SLASH12615-01XE-R datasheet(83/98 Pages) TI1

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DP83848-EP

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SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019

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Layout

8.1

Layout Guidelines

8.1.1

PCB Layout Considerations

Place the 49.9-Ω,1% resistors, and 0.1-µF decoupling capacitor, near the PHYTER TD± and RD± pins

and via directly to the Vdd plane. Stubs should be avoided on all signal traces, especially the differential

signal pairs. See Figure 8-1. Within the pairs (for example, TD+ and TD–) the trace lengths should be run

parallel to each other and matched in length. Matched lengths minimize delay differences, avoiding an

increase in common mode noise and increased EMI. See Figure 8-1.

Figure 8-1. Differential Signal Pair – Stubs

Ideally there should be no crossover or via on the signal paths. Vias present impedance discontinuities

and should be minimized. Route an entire trace pair on a single layer if possible. PCB trace lengths

should be kept as short as possible. Signal traces should not be run such that they cross a plane split.

See Figure 8-2. A signal crossing a plane split may cause unpredictable return path currents and would

likely impact signal quality as well, potentially creating EMI problems.

Figure 8-2. Differential Signal Pair-Plane Crossing

MDI signal traces should have 50 Ω to ground or 100-Ω differential controlled impedance. Many tools are

available online to calculate this.

8.1.2

PCB Layer Stacking

To meet signal integrity and performance requirements, at minimum a four layer PCB is recommended for

implementing PHYTER components in end user systems. The following layer stack-ups are recommended

for four, six, and eight-layer boards, although other options are possible.

V62/12615-01XE-R Datasheet(PDF) 83 Page - Texas Instruments