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V62/12615-01XE-R Datasheet(PDF) 29 Page - Texas Instruments |
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V62/12615-01XE-R Datasheet(HTML) 29 Page - Texas Instruments |
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29 / 98 page ![]() X1 TXD[1:0] TX_EN Valid data PMD output pair Symbol T2.26.1 T2.26.4 T2.26.2 T2.26.3 29 DP83848-EP www.ti.com SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019 Submit Documentation Feedback Product Folder Links: DP83848-EP Specifications Copyright © 2012–2019, Texas Instruments Incorporated 4.7.26 RMII Transmit Timing PARAMETER DESCRIPTION NOTES MIN TYP MAX UNIT T2.26.1 X1 clock period 50-MHz reference clock 20 ns T2.26.2 TXD[1:0], TX_EN, data setup to X1 rising 3.70 ns T2.26.3 TXD[1:0], TX_EN, data hold from X1 rising 1.70 ns T2.26.4 X1 clock to PMD output pair latency From X1 rising edge to first bit of symbol 17 bits Figure 4-27. RMII Transmit Timing |
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