V62SLASH12615-01XE-R datasheet(70/98 Pages) TI1

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DP83848-EP

SLLSEC6E – SEPTEMBER 2012 – REVISED JUNE 2019

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Detailed Description

Table 5-24. RMII and Bypass Register (RBR), Addresses 0x17 (continued)

BIT

BIT NAME

DEFAULT

DESCRIPTION

1:0

ELAST_BUF[1:0]

01, RW

Receive Elasticity Buffer:

This field controls the Receive Elasticity Buffer which allows for

frequency variation tolerance between the 50MHz RMII clock and the

recovered data. The following values indicate the tolerance in bits for

a single packet. The minimum setting allows for standard Ethernet

frame sizes at ±50ppm accuracy for both RMII and Receive clocks.

For greater frequency tolerance the packet lengths may be scaled (i.e.

for ±100ppm, the packet lengths need to be divided by 2).

00 = 14 bit tolerance (up to 16800 byte packets)

01 = 2 bit tolerance (up to 2400 byte packets)

10 = 6 bit tolerance (up to 7200 byte packets)

11 = 10 bit tolerance (up to 12000 byte packets)

5.6.2.8

LED Direct Control Register (LEDCR)

This register provides the ability to directly control any or all LED outputs. It does not provide read access

to LEDs.

Table 5-25. LED Direct Control Register (LEDCR), Address 0x18

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:6

RESERVED

0, RO

Reserved: Writes ignored, Read as 0

DRV_SPDLED

0, RW

1 = Drive value of SPDLED bit onto LED_SPD output

0 = Normal operation

DRV_LNKLED

0, RW

1 = Drive value of LNKLED bit onto LED_LNK output

0 = Normal operation

DRV_ACTLED

0, RW

1 = Drive value of ACTLED bit onto LED_ACT/COL output

0 = Normal operation

SPDLED

0, RW

Value to force on LED_SPD output

LNKLED

0, RW

Value to force on LED_LNK output

ACTLED

0, RW

Value to force on LED_ACT/COL output

5.6.2.9

PHY Control Register (PHYCR)

Table 5-26. PHY Control Register (PHYCR), Address 0x19

BIT

BIT NAME

DEFAULT

DESCRIPTION

MDIX_EN

Strap, RW

Auto-MDIX Enable:

1 = Enable Auto-neg Auto-MDIX capability

0 = Disable Auto-neg Auto-MDIX capability

The Auto-MDIX algorithm requires that the Auto-Negotiation Enable bit

in the BMCR register to be set. If Auto-Negotiation is not enabled, Auto-

MDIX should be disabled as well.

FORCE_MDIX

0, RW

Force MDIX:

1 = Force MDI pairs to cross

(Receive on TPTD pair, Transmit on TPRD pair)

0 = Normal operation

PAUSE_RX

0, RO

Pause Receive Negotiated:

Indicates that pause receive should be enabled in the MAC. Based on

ANAR[11:10] and ANLPAR[11:10] settings.

This function shall be enabled according to IEEE 802.3 Annex 28B

Table 28B-3, “Pause Resolution”, only if the Auto-Negotiated Highest

Common Denominator is a full duplex technology.

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